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authorDavid Gibson <david@gibson.dropbear.id.au>2012-11-12 16:46:49 +0000
committerAlexander Graf <agraf@suse.de>2012-12-14 13:12:53 +0100
commit044f4c8b0ee90290b6cbbc616c4be3c8aeffcaab (patch)
treeae473a71365047212c6b3a0600433e990b87c41c
parent1c97e303d4ea80a2691334b0febe87a50660f99d (diff)
downloadfocaccia-qemu-044f4c8b0ee90290b6cbbc616c4be3c8aeffcaab.tar.gz
focaccia-qemu-044f4c8b0ee90290b6cbbc616c4be3c8aeffcaab.zip
pseries: Fix incorrect initialization of interrupt controller
Currently in the reset code for the XICS interrupt controller, we
initialize the pending_priority field to 0 (most favored, by XICS
convention).  This is incorrect, since there is no pending interrupt, it
should be set to least favored - 0xff.  At the moment our XICS
implementation doesn't get hurt by this edge case, but it does confuse the
upcoming kernel XICS implementation.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
-rw-r--r--hw/xics.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/xics.c b/hw/xics.c
index 1da310653b..edf58339c0 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -495,7 +495,7 @@ static void xics_reset(void *opaque)
 
     for (i = 0; i < icp->nr_servers; i++) {
         icp->ss[i].xirr = 0;
-        icp->ss[i].pending_priority = 0;
+        icp->ss[i].pending_priority = 0xff;
         icp->ss[i].mfrr = 0xff;
         /* Make all outputs are deasserted */
         qemu_set_irq(icp->ss[i].output, 0);