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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-08-14 11:14:49 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-08-20 00:49:05 +0200 |
| commit | 1e5a7c57a577d7702c668ef9fcdc9fa4187ef8aa (patch) | |
| tree | c77cc7eec568ce1478cc1369cf75af492eedb2d6 | |
| parent | f7e3d7521b41ada97c5344914d3c9bc6ed04c82a (diff) | |
| download | focaccia-qemu-1e5a7c57a577d7702c668ef9fcdc9fa4187ef8aa.tar.gz focaccia-qemu-1e5a7c57a577d7702c668ef9fcdc9fa4187ef8aa.zip | |
linux-user/mips: Select Octeon68XX CPU for Octeon binaries
The Octeon68XX CPU is available since commit 9a6046a655
("target/mips: introduce Cavium Octeon CPU model").
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1722
Reported-by: Johnathan Hữu Trí <nhtri2003@gmail.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240814133928.6746-3-philmd@linaro.org>
| -rw-r--r-- | linux-user/mips64/target_elf.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h index ec55d8542a..ce6fb6541e 100644 --- a/linux-user/mips64/target_elf.h +++ b/linux-user/mips64/target_elf.h @@ -9,6 +9,14 @@ #define MIPS64_TARGET_ELF_H static inline const char *cpu_get_model(uint32_t eflags) { + switch (eflags & EF_MIPS_MACH) { + case EF_MIPS_MACH_OCTEON: + case EF_MIPS_MACH_OCTEON2: + case EF_MIPS_MACH_OCTEON3: + return "Octeon68XX"; + default: + break; + } if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) { return "I6400"; } |