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| author | CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> | 2025-09-01 11:17:20 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-10-05 09:01:08 -0400 |
| commit | 57ac646a2ecb2967c46febcfd0f40d396868b4dc (patch) | |
| tree | ed449739dadaba0aaeb55a5931d2baa2e7fb743c | |
| parent | ec450d185e4c885396a8e9b9bd2a435c9e0c118f (diff) | |
| download | focaccia-qemu-57ac646a2ecb2967c46febcfd0f40d396868b4dc.tar.gz focaccia-qemu-57ac646a2ecb2967c46febcfd0f40d396868b4dc.zip | |
intel_iommu: Bypass barrier wait descriptor
wait_desc with SW=0,IF=0,FN=1 must not be considered as an invalid descriptor as it is used to implement section 7.10 of the VT-d spec. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250901111630.1018573-3-clement.mathieu--drif@eviden.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/i386/intel_iommu.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 83c5e44413..4e7ad3a290 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2857,7 +2857,13 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) vtd_generate_completion_event(s); } - if (!(inv_desc->lo & (VTD_INV_DESC_WAIT_IF | VTD_INV_DESC_WAIT_SW))) { + /* + * SW=0, IF=0, FN=1 is also a valid descriptor (VT-d 7.10) + * Nothing to do as we process the descriptors in order + */ + + if (!(inv_desc->lo & (VTD_INV_DESC_WAIT_IF | VTD_INV_DESC_WAIT_SW | + VTD_INV_DESC_WAIT_FN))) { error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64 " (unknown type)", __func__, inv_desc->hi, inv_desc->lo); |