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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-03-01 10:41:07 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-05 13:22:56 +0000 |
| commit | a0ff4a879cd3198adb4213653d51a39d053ef2d6 (patch) | |
| tree | 2dbb34a34b978b0e7900f6ecae30df37953c7b4a | |
| parent | a1a85a9502b5d0011320fdf490c1d6bc2f8fdc79 (diff) | |
| download | focaccia-qemu-a0ff4a879cd3198adb4213653d51a39d053ef2d6.tar.gz focaccia-qemu-a0ff4a879cd3198adb4213653d51a39d053ef2d6.zip | |
accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | accel/tcg/cputlb.c | 5 | ||||
| -rw-r--r-- | include/exec/memattrs.h | 2 | ||||
| -rw-r--r-- | include/hw/core/cpu.h | 3 | ||||
| -rw-r--r-- | target/sparc/mmu_helper.c | 2 |
4 files changed, 5 insertions, 7 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6243bcb179..ac986cb8ea 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1145,14 +1145,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", addr, full->phys_addr, prot, mmu_idx); - read_flags = 0; + read_flags = full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |= TLB_INVALID_MASK; } - if (full->attrs.byte_swap) { - read_flags |= TLB_BSWAP; - } is_ram = memory_region_is_ram(section->mr); is_romd = memory_region_is_romd(section->mr); diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index afa885f983..14cdd8d582 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -52,8 +52,6 @@ typedef struct MemTxAttrs { unsigned int memory:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; - /* Invert endianness for this page */ - unsigned int byte_swap:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d0e345419f..ec14f74ce5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -230,6 +230,9 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + /* Additional tlb flags requested by tlb_fill. */ + uint8_t tlb_fill_flags; + /* * Additional tlb flags for use by the slow path. If non-zero, * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 5170a668bb..e7b1997d54 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full, int do_fault = 0; if (TTE_IS_IE(env->dtlb[i].tte)) { - full->attrs.byte_swap = true; + full->tlb_fill_flags |= TLB_BSWAP; } /* access ok? */ |