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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-02-09 08:57:50 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-02-15 15:53:12 +0100 |
| commit | c2bb8e1bcccb9d8228bc2ec55bbcbdb8f1ce774c (patch) | |
| tree | 790164f2c7def4b7980769f8c52157ec136815f5 | |
| parent | b267e78908afd450433ef44d840c4ff30ba37676 (diff) | |
| download | focaccia-qemu-c2bb8e1bcccb9d8228bc2ec55bbcbdb8f1ce774c.tar.gz focaccia-qemu-c2bb8e1bcccb9d8228bc2ec55bbcbdb8f1ce774c.zip | |
target/mips: Remove CPUMIPSState::saarp field
This field is never set, so remove the unreachable code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240209090513.9401-5-philmd@linaro.org>
| -rw-r--r-- | hw/misc/mips_itu.c | 6 | ||||
| -rw-r--r-- | target/mips/cpu.h | 1 |
2 files changed, 0 insertions, 7 deletions
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index db1220f8e0..d259a88d22 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -516,7 +516,6 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s = MIPS_ITU(dev); - CPUMIPSState *env; if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -533,11 +532,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) return; } - env = &MIPS_CPU(s->cpu0)->env; - if (env->saarp) { - s->saar = env->CP0_SAAR; - } - s->cell = g_new(ITCStorageCell, get_num_cells(s)); } diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d54e9a4a1c..ef1d9f279c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1174,7 +1174,6 @@ typedef struct CPUArchState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ - int saarp; /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; |