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| author | Ajax <commial@gmail.com> | 2017-07-21 17:35:05 +0200 |
|---|---|---|
| committer | Ajax <commial@gmail.com> | 2017-07-21 17:35:05 +0200 |
| commit | f1d0b9388cec285717b28d1367f6667a9949774c (patch) | |
| tree | 0b305e1bf59fd24fab6f6c46352c94079375a548 | |
| parent | 6332dcc344b28e9a8e8b17c718364e2c5c1ad235 (diff) | |
| download | miasm-f1d0b9388cec285717b28d1367f6667a9949774c.tar.gz miasm-f1d0b9388cec285717b28d1367f6667a9949774c.zip | |
Add support for multi-ret on cdecl / systemV x86 ABI
| -rw-r--r-- | miasm2/arch/x86/jit.py | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index d39f1f38..50501060 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -135,10 +135,12 @@ class jitter_x86_32(jitter): args = [self.get_stack_arg(i) for i in xrange(n_args)] return ret_ad, args - def func_ret_cdecl(self, ret_addr, ret_value=None): + def func_ret_cdecl(self, ret_addr, ret_value1=None, ret_value2=None): self.pc = self.cpu.EIP = ret_addr - if ret_value is not None: - self.cpu.EAX = ret_value + if ret_value1 is not None: + self.cpu.EAX = ret_value1 + if ret_value2 is not None: + self.cpu.EDX = ret_value2 get_arg_n_cdecl = get_stack_arg |