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authorptitSeb <sebastien.chev@gmail.com>2025-09-17 17:41:48 +0200
committerptitSeb <sebastien.chev@gmail.com>2025-09-17 17:41:48 +0200
commit78833500c8b3ebdb13803a8da5bb61f34628a2d2 (patch)
tree6993116bf34d2b769851c71f4e82a71accb9c6ba /src/dynarec
parent1a58da4315570f322c3a4ec35e17b1da87d929fe (diff)
downloadbox64-78833500c8b3ebdb13803a8da5bb61f34628a2d2.tar.gz
box64-78833500c8b3ebdb13803a8da5bb61f34628a2d2.zip
[ARM64_DYNAREC] Temporarily disable Atomic path for F0 0F B1, as it avoid some games random freeze (like HorizonZeroDawn or Cyberpunk2077)
Diffstat (limited to 'src/dynarec')
-rw-r--r--src/dynarec/arm64/dynarec_arm64_f0.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/dynarec/arm64/dynarec_arm64_f0.c b/src/dynarec/arm64/dynarec_arm64_f0.c
index 93180260..2e5f82ff 100644
--- a/src/dynarec/arm64/dynarec_arm64_f0.c
+++ b/src/dynarec/arm64/dynarec_arm64_f0.c
@@ -350,7 +350,10 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                     }
                                 }
                                 // Aligned version
-                                if(cpuext.atomics) {
+                                // disabling use of atomics for now, as it seems to make (at least)
+                                //  HorizonZeroDawn and Cyberpunk2077 (both from GoG) unstable
+                                //  but why?!
+                                if(cpuext.atomics && 0) {
                                     UFLAG_IF {
                                         MOVxw_REG(x1, xRAX);
                                         CASALxw(x1, gd, wback);
@@ -394,7 +397,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                 // Common part (and fallback for EAX != Ed)
                                 UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, x1, x3, x4, x5); MOVxw_REG(xRAX, x1);}
                                 else {
-                                    if(!ALIGNED_ATOMICxw || !cpuext.atomics)
+                                    if(!ALIGNED_ATOMICxw || !(cpuext.atomics && 0))
                                         MOVxw_REG(xRAX, x1);    // upper par of RAX will be erase on 32bits, no mater what
                                 }
                             }