[LA64_DYNAREC]Add basic avx support for la64. (#2745)

* basic infra for avx
    * some basic ops for avx
	VMOVDQU/VMOVDQA/VMOVUPS/VMOVAPS/VMOVUPD/VMOVAPD
	VZEROUPPER/VZEROALL
	VMOVD/VMOVSD/VMOVSS
	VINSERTF128/VINSERTI128/VEXTRACTF128/VEXTRACTI128
	VBROADCASTSS/VBROADCASTSD/VBROADCASTF128

15 files changed, 5578 insertions, 70 deletions

diff --git a/src/dynarec/la64/dynarec_la64_00.c b/src/dynarec/la64/dynarec_la64_00.c
index 20b7a597..9ec6d4b1 100644
--- a/src/dynarec/la64/dynarec_la64_00.c
+++ b/src/dynarec/la64/dynarec_la64_00.c
@@ -1868,6 +1868,45 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
             *need_epilog = 0;
             *ok = 0;
             break;
+        case 0xC4:
+            nextop = F8;
+            if (rex.is32bits && !(MODREG)) {
+                DEFAULT;
+            } else {
+                vex_t vex = { 0 };
+                vex.rex = rex;
+                u8 = nextop;
+                vex.m = u8 & 0b00011111;
+                vex.rex.b = (u8 & 0b00100000) ? 0 : 1;
+                vex.rex.x = (u8 & 0b01000000) ? 0 : 1;
+                vex.rex.r = (u8 & 0b10000000) ? 0 : 1;
+                u8 = F8;
+                vex.p = u8 & 0b00000011;
+                vex.l = (u8 >> 2) & 1;
+                vex.v = ((~u8) >> 3) & 0b1111;
+                vex.rex.w = (u8 >> 7) & 1;
+                addr = dynarec64_AVX(dyn, addr, ip, ninst, vex, ok, need_epilog);
+            }
+            break;
+        case 0xC5:
+            nextop = F8;
+            if (rex.is32bits && !(MODREG)) {
+                DEFAULT;
+            } else {
+                vex_t vex = { 0 };
+                vex.rex = rex;
+                u8 = nextop;
+                vex.p = u8 & 0b00000011;
+                vex.l = (u8 >> 2) & 1;
+                vex.v = ((~u8) >> 3) & 0b1111;
+                vex.rex.r = (u8 & 0b10000000) ? 0 : 1;
+                vex.rex.b = 0;
+                vex.rex.x = 0;
+                vex.rex.w = 0;
+                vex.m = VEX_M_0F;
+                addr = dynarec64_AVX(dyn, addr, ip, ninst, vex, ok, need_epilog);
+            }
+            break;
         case 0xC6:
             INST_NAME("MOV Eb, Ib");
             nextop = F8;
diff --git a/src/dynarec/la64/dynarec_la64_avx.c b/src/dynarec/la64/dynarec_la64_avx.c
new file mode 100644
index 00000000..1a8a14a7
--- /dev/null
+++ b/src/dynarec/la64/dynarec_la64_avx.c
@@ -0,0 +1,81 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "box64cpu.h"
+#include "emu/x64emu_private.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "dynarec_la64_functions.h"
+#include "dynarec_la64_helper.h"
+
+static const char* avx_prefix_string(uint16_t p)
+{
+    switch (p) {
+        case VEX_P_NONE: return "0";
+        case VEX_P_66: return "66";
+        case VEX_P_F2: return "F2";
+        case VEX_P_F3: return "F3";
+        default: return "??";
+    }
+}
+static const char* avx_map_string(uint16_t m)
+{
+    switch (m) {
+        case VEX_M_NONE: return "0";
+        case VEX_M_0F: return "0F";
+        case VEX_M_0F38: return "0F38";
+        case VEX_M_0F3A: return "0F3A";
+        default: return "??";
+    }
+}
+
+uintptr_t dynarec64_AVX(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = PK(0);
+    rex_t rex = vex.rex;
+
+
+    if ((vex.m == VEX_M_0F) && (vex.p == VEX_P_NONE))
+        addr = dynarec64_AVX_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    // else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_NONE))
+    //     addr = dynarec64_AVX_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if ((vex.m == VEX_M_0F) && (vex.p == VEX_P_66))
+        addr = dynarec64_AVX_66_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if ((vex.m == VEX_M_0F) && (vex.p == VEX_P_F2))
+        addr = dynarec64_AVX_F2_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if ((vex.m == VEX_M_0F) && (vex.p == VEX_P_F3))
+        addr = dynarec64_AVX_F3_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if ((vex.m == VEX_M_0F38) && (vex.p == VEX_P_66))
+        addr = dynarec64_AVX_66_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if ((vex.m == VEX_M_0F3A) && (vex.p == VEX_P_66))
+        addr = dynarec64_AVX_66_0F3A(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    // else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F2))
+    //     addr = dynarec64_AVX_F2_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    // else if( (vex.m==VEX_M_0F3A) && (vex.p==VEX_P_F2))
+    //     addr = dynarec64_AVX_F2_0F3A(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    // else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F3))
+    //     addr = dynarec64_AVX_F3_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else {
+        DEFAULT;
+    }
+
+    if((*ok==-1) && (BOX64ENV(dynarec_log)>=LOG_INFO || dyn->need_dump || BOX64ENV(dynarec_missing)))
+        if(!dyn->size || BOX64ENV(dynarec_log)>LOG_INFO || dyn->need_dump) {
+            dynarec_log(LOG_NONE, "  Dynarec unimplemented VEX opcode size %d prefix %s map %s opcode %02X\n", 128<<vex.l, avx_prefix_string(vex.p), avx_map_string(vex.m), opcode);
+    }
+    return addr;
+}
\ No newline at end of file
diff --git a/src/dynarec/la64/dynarec_la64_avx_0f.c b/src/dynarec/la64/dynarec_la64_avx_0f.c
new file mode 100644
index 00000000..ec260232
--- /dev/null
+++ b/src/dynarec/la64/dynarec_la64_avx_0f.c
@@ -0,0 +1,188 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "env.h"
+#include "box64context.h"
+#include "box64cpu.h"
+#include "emu/x64emu_private.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "dynarec_la64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch (opcode) {
+        case 0x10:
+            INST_NAME("VMOVUPS Gx, Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETGY_empty_EY_xy(q0, q1, 0);
+                if (vex.l) {
+                    XVOR_V(q0, q1, q1);
+                } else {
+                    VOR_V(q0, q1, q1);
+                }
+            } else {
+                GETGYxy_empty(q0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVLD(q0, ed, fixedaddress);
+                } else {
+                    VLD(q0, ed, fixedaddress);
+                }
+            }
+            break;
+        case 0x11:
+            INST_NAME("VMOVUPS Ex, Gx");
+            nextop = F8;
+            GETGYxy(q0, 0);
+            if (MODREG) {
+                GETEYxy_empty(q1, 0);
+                if (vex.l) {
+                    XVOR_V(q1, q0, q0);
+                } else {
+                    VOR_V(q1, q0, q0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, x5, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVST(q0, ed, fixedaddress);
+                } else {
+                    VST(q0, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0x28:
+            INST_NAME("VMOVAPS Gx, Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETGY_empty_EY_xy(q0, q1, 0);
+                if (vex.l) {
+                    XVOR_V(q0, q1, q1);
+                } else {
+                    VOR_V(q0, q1, q1);
+                }
+            } else {
+                GETGYxy_empty(q0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, x5, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVLD(q0, ed, fixedaddress);
+                } else {
+                    VLD(q0, ed, fixedaddress);
+                }
+            }
+            break;
+        case 0x29:
+            INST_NAME("VMOVAPS Ex, Gx");
+            nextop = F8;
+            GETGYxy(q0, 0);
+            if (MODREG) {
+                GETEYxy_empty(q1, 0);
+                if (vex.l) {
+                    XVOR_V(q1, q0, q0);
+                } else {
+                    VOR_V(q1, q0, q0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, x5, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVST(q0, ed, fixedaddress);
+                } else {
+                    VST(q0, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0x77:
+            if (!vex.l) {
+                INST_NAME("VZEROUPPER");
+                if (vex.v != 0) {
+                    UDF();
+                } else {
+                    q2 = fpu_get_scratch(dyn);
+                    XVXOR_V(q2, q2, q2);
+                    for (int i = 0; i < (rex.is32bits ? 8 : 16); ++i) {
+                        if (dyn->lsx.avxcache[i].v != -1 ){
+                            // avx used register
+                            if(dyn->lsx.avxcache[i].width == LSX_AVX_WIDTH_256) {
+                                // 256 width, fill upper 128bits with zero.
+                                q1 = avx_get_reg(dyn, ninst, x1, i, 1, LSX_AVX_WIDTH_256); // mark reg write (dirty)
+                                XVPERMI_Q(q1, q2, XVPERMI_IMM_4_0(0, 2));
+                            } else {
+                                // 128 width, lazy save.
+                                q1 = avx_get_reg(dyn, ninst, x1, i, 1, LSX_AVX_WIDTH_128); // mark reg write (dirty)
+                                dyn->lsx.avxcache[i].zero_upper = 1;
+                            }
+                        }else {
+                            // SSE register or unused register, store 128bit zero to x64emu_t.ymm[]
+                            VST(q2, xEmu, offsetof(x64emu_t, ymm[i]));
+                        }
+                    }
+                    SMWRITE2();
+                }
+            } else {
+                INST_NAME("VZEROALL");
+                if (vex.v != 0) {
+                    UDF();
+                } else {
+                    for (int i = 0; i < (rex.is32bits ? 8 : 16); ++i) {
+                        q0 = avx_get_reg_empty(dyn, ninst, x1, i, LSX_AVX_WIDTH_256);
+                        XVXOR_V(q0, q0, q0);
+                    }
+                }
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
diff --git a/src/dynarec/la64/dynarec_la64_avx_66_0f.c b/src/dynarec/la64/dynarec_la64_avx_66_0f.c
new file mode 100644
index 00000000..f8c4963c
--- /dev/null
+++ b/src/dynarec/la64/dynarec_la64_avx_66_0f.c
@@ -0,0 +1,225 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "env.h"
+#include "box64context.h"
+#include "box64cpu.h"
+#include "emu/x64emu_private.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "dynarec_la64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_66_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch (opcode) {
+        case 0x10:
+            INST_NAME("VMOVUPD Gx, Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETGY_empty_EY_xy(q0, q1, 0);
+                if (vex.l) {
+                    XVOR_V(q0, q1, q1);
+                } else {
+                    VOR_V(q0, q1, q1);
+                }
+            } else {
+                GETGYxy_empty(q0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVLD(q0, ed, fixedaddress);
+                } else {
+                    VLD(q0, ed, fixedaddress);
+                }
+            }
+            break;
+        case 0x11:
+            INST_NAME("VMOVUPD Ex, Gx");
+            nextop = F8;
+            GETGYxy(q0, 0);
+            if (MODREG) {
+                GETEYxy_empty(q1, 0);
+                if (vex.l) {
+                    XVOR_V(q1, q0, q0);
+                } else {
+                    VOR_V(q1, q0, q0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, x5, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVST(q0, ed, fixedaddress);
+                } else {
+                    VST(q0, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0x28:
+            INST_NAME("VMOVAPD Gx, Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETGY_empty_EY_xy(q0, q1, 0);
+                if (vex.l) {
+                    XVOR_V(q0, q1, q1);
+                } else {
+                    VOR_V(q0, q1, q1);
+                }
+            } else {
+                GETGYxy_empty(q0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVLD(q0, ed, fixedaddress);
+                } else {
+                    VLD(q0, ed, fixedaddress);
+                }
+            }
+            break;
+        case 0x29:
+            INST_NAME("VMOVAPD Ex, Gx");
+            nextop = F8;
+            GETGYxy(q0, 0);
+            if (MODREG) {
+                GETEYxy_empty(q1, 0);
+                if (vex.l) {
+                    XVOR_V(q1, q0, q0);
+                } else {
+                    VOR_V(q1, q0, q0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, x5, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVST(q0, ed, fixedaddress);
+                } else {
+                    VST(q0, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0x6E:
+            INST_NAME("VMOVD Gx, Ed");
+            nextop = F8;
+            GETED(0);
+            GETGYx_empty(q0);
+            XVXOR_V(q0, q0, q0);
+            if (rex.w) {
+                XVINSGR2VR_D(q0, ed, 0);
+            } else {
+                XVINSGR2VR_W(q0, ed, 0);
+            }
+            YMM_UNMARK_UPPER_ZERO(q0);
+            break;
+        case 0x6F:
+            INST_NAME("VMOVDQA Gx, Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETGY_empty_EY_xy(q0, q1, 0);
+                if (vex.l) {
+                    XVOR_V(q0, q1, q1);
+                } else {
+                    VOR_V(q0, q1, q1);
+                }
+            } else {
+                GETGYxy_empty(q0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVLD(q0, ed, fixedaddress);
+                } else {
+                    VLD(q0, ed, fixedaddress);
+                }
+            }
+            break;
+        case 0x7E:
+            INST_NAME("VMOVD Ed, Gx");
+            nextop = F8;
+            GETGYx(v0, 0);
+            if (MODREG) {
+                ed = TO_NAT((nextop & 0x07) + (rex.b << 3));
+                if (rex.w) {
+                    VPICKVE2GR_D(ed, v0, 0);
+                } else {
+                    VPICKVE2GR_W(ed, v0, 0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                if (rex.w) {
+                    FST_D(v0, ed, fixedaddress);
+                } else {
+                    FST_S(v0, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0x7F:
+            INST_NAME("VMOVDQA Ex, Gx");
+            nextop = F8;
+            GETGYxy(q0, 0);
+            if (MODREG) {
+                GETEYxy_empty(q1, 0);
+                if (vex.l) {
+                    XVOR_V(q1, q0, q0);
+                } else {
+                    VOR_V(q1, q0, q0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, x5, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVST(q0, ed, fixedaddress);
+                } else {
+                    VST(q0, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
diff --git a/src/dynarec/la64/dynarec_la64_avx_66_0f38.c b/src/dynarec/la64/dynarec_la64_avx_66_0f38.c
new file mode 100644
index 00000000..752cd308
--- /dev/null
+++ b/src/dynarec/la64/dynarec_la64_avx_66_0f38.c
@@ -0,0 +1,92 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "env.h"
+#include "box64context.h"
+#include "box64cpu.h"
+#include "emu/x64emu_private.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "dynarec_la64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_66_0F38(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch (opcode) {
+        case 0x18:
+            INST_NAME("VBROADCASTSS Gx, Ex");
+            nextop = F8;
+            GETEYSS(q2, 0, 0);
+            GETGYxy_empty(q0);
+            if(vex.l){
+                XVREPLVE0_W(q0, q2);
+            }else{
+                VREPLVE_W(q0, q2, 0);
+            }
+            break;
+        case 0x19:
+            INST_NAME("VBROADCASTSD Gx, Ex");
+            nextop = F8;
+            GETEYSD(q2, 0, 0);
+            GETGYxy_empty(q0);            
+            if(vex.l){
+                XVREPLVE0_D(q0, q2);
+            }else{
+                VREPLVE_D(q0, q2, 0);
+            }
+            break;
+        case 0x1A:
+            INST_NAME("VBROADCASTF128 Gx, Ex");
+            nextop = F8;
+            GETGY_empty_EY_xy(q0, q2, 0);
+            XVREPLVE0_Q(q0, q2);
+            break;
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
diff --git a/src/dynarec/la64/dynarec_la64_avx_66_0f3a.c b/src/dynarec/la64/dynarec_la64_avx_66_0f3a.c
new file mode 100644
index 00000000..1310cac2
--- /dev/null
+++ b/src/dynarec/la64/dynarec_la64_avx_66_0f3a.c
@@ -0,0 +1,98 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "env.h"
+#include "box64context.h"
+#include "box64cpu.h"
+#include "emu/x64emu_private.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "dynarec_la64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_66_0F3A(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch (opcode) {
+        case 0x18:
+        case 0x38:
+            if (opcode == 0x18) {
+                INST_NAME("VINSERTF128 Gx, Vx, Ex, imm8");
+            } else {
+                INST_NAME("VINSERTI128 Gx, Vx, Ex, imm8");
+            }
+            nextop = F8;
+            GETGY_empty_VYEY_xy(q0, q1, q2, 1);
+            u8 = F8;
+            XVOR_V(q0, q1, q1);
+            XVPERMI_Q(q0, q2, (u8&1) == 0 ? 0b00110000 : 0b00000010);
+            break;
+        case 0x19:
+        case 0x39:
+            if (opcode == 0x19) {
+                INST_NAME("VEXTRACTF128 Ex, Gx, imm8");
+            } else {
+                INST_NAME("VEXTRACTI128 Ex, Gx, imm8");
+            }
+            nextop = F8;
+            GETEY_GY_xy(q1, q0, 1);
+            u8 = F8;
+            if (MODREG) {
+                XVPERMI_Q(q1, q0, (u8&1) == 0 ? XVPERMI_IMM_4_0(3, 0) : XVPERMI_IMM_4_0(3, 1));
+            } else {
+                if ((u8&1) == 1) {
+                    XVPERMI_Q(q1, q0, XVPERMI_IMM_4_0(3, 1));
+                    VST(q1, ed, fixedaddress);
+                } else {
+                    VST(q0, ed, fixedaddress);
+                }
+            }
+            break;
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
diff --git a/src/dynarec/la64/dynarec_la64_avx_f2_0f.c b/src/dynarec/la64/dynarec_la64_avx_f2_0f.c
new file mode 100644
index 00000000..6d6f8209
--- /dev/null
+++ b/src/dynarec/la64/dynarec_la64_avx_f2_0f.c
@@ -0,0 +1,103 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "env.h"
+#include "box64context.h"
+#include "box64cpu.h"
+#include "emu/x64emu_private.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "dynarec_la64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_F2_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u, u64;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch (opcode) {
+
+        case 0x10:
+            INST_NAME("VMOVSD Gx, [Vx,] Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETVYx(q1, 0);
+                GETEYSD(q2, 0, 0);
+                GETGYx_empty(q0);
+                if (gd != vex.v) VOR_V(q0, q1, q1);
+                VEXTRINS_D(q0, q2, 0);
+            } else {
+                GETEYSD(q2, 0, 0);
+                GETGYx_empty(q0);                
+                XVXOR_V(q0, q0, q0);
+                XVINSVE0_D(q0, q2, 0);
+                YMM_UNMARK_UPPER_ZERO(q0);
+            }
+            break;
+        case 0x11:
+            INST_NAME("VMOVSD Ex, [Vx,] Gx");
+            nextop = F8;
+            GETGYx(q2, 0);
+            if (MODREG) {
+                if (ed == vex.v) {
+                    GETEYSD(q0, 1, 0);
+                    VEXTRINS_D(q0, q2, 0);
+                } else {
+                    GETVYx(q1, 0);
+                    GETEYSD(q0, 1, 0);
+                    VOR_V(q0, q1, q1);
+                    VEXTRINS_D(q0, q2, 0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                FST_D(q2, ed, fixedaddress);
+                SMWRITE2();
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
diff --git a/src/dynarec/la64/dynarec_la64_avx_f3_0f.c b/src/dynarec/la64/dynarec_la64_avx_f3_0f.c
new file mode 100644
index 00000000..d9ad1413
--- /dev/null
+++ b/src/dynarec/la64/dynarec_la64_avx_f3_0f.c
@@ -0,0 +1,131 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "env.h"
+#include "box64context.h"
+#include "box64cpu.h"
+#include "emu/x64emu_private.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "dynarec_la64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_F3_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2, gback, vback;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u, u64;
+    int64_t j64;
+    int64_t fixedaddress, gdoffset, vxoffset;
+    int unscaled;
+
+    rex_t rex = vex.rex;
+
+    switch (opcode) {
+        case 0x10:
+            INST_NAME("VMOVSS Gx, [Vx,] Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETVYx(q1, 0);
+                GETEYSS(q2, 0, 0);
+                GETGYx_empty(q0);                
+                if ( !gd == vex.v) VOR_V(q0, q1, q1);
+                VEXTRINS_W(q0, q2, 0);
+            } else {
+                GETEYSS(q2, 0, 0);
+                GETGYx_empty(q0);
+                XVXOR_V(q0, q0, q0);
+                XVINSVE0_W(q0, q2, 0);
+                YMM_UNMARK_UPPER_ZERO(q0);
+            }
+            break;
+        case 0x11:
+            INST_NAME("VMOVSS Ex, [Vx,] Gx");
+            nextop = F8;
+            GETGYx(q2, 0);
+            if (MODREG) {
+                if (ed == vex.v) {
+                    GETEYSS(q0, 1, 0);
+                    VEXTRINS_W(q0, q2, 0);
+                } else {
+                    GETVYx(q1, 0);
+                    GETEYSS(q0, 1, 0);
+                    VOR_V(q0, q1, q1);
+                    VEXTRINS_W(q0, q2, 0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                FST_S(q2, ed, fixedaddress);
+                SMWRITE2();
+            }
+            break;
+        case 0x6F:
+            INST_NAME("VMOVDQU Gx, Ex");
+            nextop = F8;
+            if (MODREG) {
+                GETGY_empty_EY_xy(q0, q1, 0);
+                if (vex.l) {
+                    XVOR_V(q0, q1, q1);
+                } else {
+                    VOR_V(q0, q1, q1);
+                }
+            } else {
+                GETGYxy_empty(q0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVLD(q0, ed, fixedaddress);
+                } else {
+                    VLD(q0, ed, fixedaddress);
+                }
+            }
+            break;
+        case 0x7F:
+            INST_NAME("VMOVDQU Ex, Gx");
+            nextop = F8;
+            GETGYxy(q0, 0);
+            if (MODREG) {
+                GETEYxy_empty(q1, 0);
+                if (vex.l) {
+                    XVOR_V(q1, q0, q0);
+                } else {
+                    VOR_V(q1, q0, q0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, x5, &fixedaddress, rex, NULL, 1, 0);
+                if (vex.l) {
+                    XVST(q0, ed, fixedaddress);
+                } else {
+                    VST(q0, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
\ No newline at end of file
diff --git a/src/dynarec/la64/dynarec_la64_functions.c b/src/dynarec/la64/dynarec_la64_functions.c
index 35474f5c..2cb1b8dd 100644
--- a/src/dynarec/la64/dynarec_la64_functions.c
+++ b/src/dynarec/la64/dynarec_la64_functions.c
@@ -74,6 +74,19 @@ int fpu_get_reg_xmm(dynarec_la64_t* dyn, int t, int xmm)
     return i;
 }
 
+// Get an YMM quad reg
+int fpu_get_reg_ymm(dynarec_la64_t* dyn, int t, int ymm)
+{
+    int i;
+    i = XMM0 + ymm;
+
+    dyn->lsx.fpuused[i] = 1;
+    dyn->lsx.lsxcache[i].t = t;
+    dyn->lsx.lsxcache[i].n = ymm;
+    dyn->lsx.news |= (1 << i);
+    return i;
+}
+
 // Reset fpu regs counter
 static void fpu_reset_reg_lsxcache(lsxcache_t* lsx)
 {
@@ -145,6 +158,7 @@ int fpuCacheNeedsTransform(dynarec_la64_t* dyn, int ninst)
                 if (dyn->insts[ninst].lsx.lsxcache[i].n != cache_i2.lsxcache[i].n) {    // not the same x64 reg
                     ret = 1;
                 } else if (dyn->insts[ninst].lsx.lsxcache[i].t == LSX_CACHE_XMMR && cache_i2.lsxcache[i].t == LSX_CACHE_XMMW) { /* nothing */
+                } else if (dyn->insts[ninst].lsx.lsxcache[i].t == LSX_CACHE_YMMR && cache_i2.lsxcache[i].t == LSX_CACHE_YMMW) { /* nothing */
                 } else
                     ret = 1;
             }
@@ -223,6 +237,8 @@ void lsxcacheUnwind(lsxcache_t* cache)
         cache->x87reg[i] = 0;
         cache->ssecache[i * 2].v = -1;
         cache->ssecache[i * 2 + 1].v = -1;
+        cache->avxcache[i * 2].v = -1;
+        cache->avxcache[i * 2 + 1].v = -1;
     }
     int x87reg = 0;
     for (int i = 0; i < 24; ++i) {
@@ -240,6 +256,12 @@ void lsxcacheUnwind(lsxcache_t* cache)
                     cache->ssecache[cache->lsxcache[i].n].write = (cache->lsxcache[i].t == LSX_CACHE_XMMW) ? 1 : 0;
                     ++cache->fpu_reg;
                     break;
+                case LSX_CACHE_YMMR:
+                case LSX_CACHE_YMMW:
+                    cache->avxcache[cache->lsxcache[i].n].reg = i;
+                    cache->avxcache[cache->lsxcache[i].n].write = (cache->lsxcache[i].t == LSX_CACHE_YMMW) ? 1 : 0;
+                    ++cache->fpu_reg;
+                    break;
                 case LSX_CACHE_ST_F:
                 case LSX_CACHE_ST_D:
                 case LSX_CACHE_ST_I64:
@@ -269,6 +291,8 @@ const char* getCacheName(int t, int n)
         case LSX_CACHE_MM: sprintf(buff, "MM%d", n); break;
         case LSX_CACHE_XMMW: sprintf(buff, "XMM%d", n); break;
         case LSX_CACHE_XMMR: sprintf(buff, "xmm%d", n); break;
+        case LSX_CACHE_YMMW: sprintf(buff, "YMM%d", n); break;
+        case LSX_CACHE_YMMR: sprintf(buff, "ymm%d", n); break;        
         case LSX_CACHE_SCR: sprintf(buff, "Scratch"); break;
         case LSX_CACHE_NONE: buff[0] = '\0'; break;
     }
@@ -385,6 +409,8 @@ void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t r
             case LSX_CACHE_MM: length += sprintf(buf + length, " D%d:%s", ii, getCacheName(dyn->insts[ninst].lsx.lsxcache[ii].t, dyn->insts[ninst].lsx.lsxcache[ii].n)); break;
             case LSX_CACHE_XMMW: length += sprintf(buf + length, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].lsx.lsxcache[ii].t, dyn->insts[ninst].lsx.lsxcache[ii].n)); break;
             case LSX_CACHE_XMMR: length += sprintf(buf + length, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].lsx.lsxcache[ii].t, dyn->insts[ninst].lsx.lsxcache[ii].n)); break;
+            case LSX_CACHE_YMMW: length += sprintf(buf + length, " Q%d:%s%s", ii, getCacheName(dyn->insts[ninst].lsx.lsxcache[ii].t, dyn->insts[ninst].lsx.lsxcache[ii].n), dyn->insts[ninst].lsx.avxcache[dyn->insts[ninst].lsx.lsxcache[ii].n].zero_upper==1?"-UZ":""); break;
+            case LSX_CACHE_YMMR: length += sprintf(buf + length, " Q%d:%s%s", ii, getCacheName(dyn->insts[ninst].lsx.lsxcache[ii].t, dyn->insts[ninst].lsx.lsxcache[ii].n), dyn->insts[ninst].lsx.avxcache[dyn->insts[ninst].lsx.lsxcache[ii].n].zero_upper==1?"-UZ":""); break;
             case LSX_CACHE_SCR: length += sprintf(buf + length, " D%d:%s", ii, getCacheName(dyn->insts[ninst].lsx.lsxcache[ii].t, dyn->insts[ninst].lsx.lsxcache[ii].n)); break;
             case LSX_CACHE_NONE:
             default: break;
@@ -515,12 +541,18 @@ static void sse_reset(lsxcache_t* lsx)
     for (int i = 0; i < 16; ++i)
         lsx->ssecache[i].v = -1;
 }
+static void avx_reset(lsxcache_t* lsx)
+{
+    for (int i = 0; i < 16; ++i)
+        lsx->avxcache[i].v = -1;
+}
 
 void fpu_reset(dynarec_la64_t* dyn)
 {
     x87_reset(&dyn->lsx);
     mmx_reset(&dyn->lsx);
     sse_reset(&dyn->lsx);
+    avx_reset(&dyn->lsx);
     fpu_reset_reg(dyn);
 }
 
@@ -528,6 +560,7 @@ void fpu_reset_ninst(dynarec_la64_t* dyn, int ninst)
 {
     // TODO: x87 and mmx
     sse_reset(&dyn->insts[ninst].lsx);
+    avx_reset(&dyn->insts[ninst].lsx);
     fpu_reset_reg_lsxcache(&dyn->insts[ninst].lsx);
 }
 
diff --git a/src/dynarec/la64/dynarec_la64_functions.h b/src/dynarec/la64/dynarec_la64_functions.h
index 17b2280f..4b96b497 100644
--- a/src/dynarec/la64/dynarec_la64_functions.h
+++ b/src/dynarec/la64/dynarec_la64_functions.h
@@ -14,6 +14,8 @@ int fpu_get_scratch(dynarec_la64_t* dyn);
 void fpu_reset_scratch(dynarec_la64_t* dyn);
 // Get an XMM quad reg
 int fpu_get_reg_xmm(dynarec_la64_t* dyn, int t, int xmm);
+// Get an YMM quad reg
+int fpu_get_reg_ymm(dynarec_la64_t* dyn, int t, int ymm);
 // Free a FPU/MMX/XMM reg
 void fpu_free_reg(dynarec_la64_t* dyn, int reg);
 // Reset fpu regs counter
diff --git a/src/dynarec/la64/dynarec_la64_helper.c b/src/dynarec/la64/dynarec_la64_helper.c
index 6fa48606..f119c984 100644
--- a/src/dynarec/la64/dynarec_la64_helper.c
+++ b/src/dynarec/la64/dynarec_la64_helper.c
@@ -883,6 +883,11 @@ int sse_get_reg(dynarec_la64_t* dyn, int ninst, int s1, int a, int forwrite)
         }
         return dyn->lsx.ssecache[a].reg;
     }
+    // migrate from avx to sse
+    if (dyn->lsx.avxcache[a].v != -1) {
+        avx_reflect_reg_upper128(dyn, ninst, a, forwrite);
+        dyn->lsx.avxcache[a].v = -1;
+    }
     dyn->lsx.ssecache[a].reg = fpu_get_reg_xmm(dyn, forwrite ? LSX_CACHE_XMMW : LSX_CACHE_XMMR, a);
     int ret = dyn->lsx.ssecache[a].reg;
     dyn->lsx.ssecache[a].write = forwrite;
@@ -898,6 +903,11 @@ int sse_get_reg_empty(dynarec_la64_t* dyn, int ninst, int s1, int a)
         dyn->lsx.lsxcache[dyn->lsx.ssecache[a].reg].t = LSX_CACHE_XMMW;
         return dyn->lsx.ssecache[a].reg;
     }
+    // migrate from avx to sse
+    if (dyn->lsx.avxcache[a].v != -1) {
+        avx_reflect_reg_upper128(dyn, ninst, a, 1);
+        dyn->lsx.avxcache[a].v = -1;
+    }
     dyn->lsx.ssecache[a].reg = fpu_get_reg_xmm(dyn, LSX_CACHE_XMMW, a);
     dyn->lsx.ssecache[a].write = 1; // it will be write...
     return dyn->lsx.ssecache[a].reg;
@@ -929,16 +939,26 @@ void sse_purge07cache(dynarec_la64_t* dyn, int ninst, int s1)
 {
     int old = -1;
     for (int i = 0; i < 8; ++i)
-        if (dyn->lsx.ssecache[i].v != -1) {
+        if (dyn->lsx.ssecache[i].v != -1 || dyn->lsx.avxcache[i].v != -1) {
             if (old == -1) {
                 MESSAGE(LOG_DUMP, "\tPurge XMM0..7 Cache ------\n");
                 ++old;
             }
-            if (dyn->lsx.lsxcache[dyn->lsx.ssecache[i].reg].t == LSX_CACHE_XMMW) {
+            if (dyn->lsx.lsxcache[dyn->lsx.avxcache[i].reg].t == LSX_CACHE_YMMW) {
+                VST(dyn->lsx.avxcache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+                if(dyn->lsx.avxcache[i].zero_upper == 1){
+                    XVXOR_V(SCRATCH, SCRATCH, SCRATCH);
+                }else{
+                    XVPERMI_Q(SCRATCH, dyn->lsx.avxcache[i].reg, XVPERMI_IMM_4_0(0, 1));
+                }
+                VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[i]));
+                fpu_free_reg(dyn, dyn->lsx.avxcache[i].reg);
+                dyn->lsx.avxcache[i].v = -1;
+            } else if (dyn->lsx.lsxcache[dyn->lsx.ssecache[i].reg].t == LSX_CACHE_XMMW) {
                 VST(dyn->lsx.ssecache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+                fpu_free_reg(dyn, dyn->lsx.ssecache[i].reg);
+                dyn->lsx.ssecache[i].v = -1;
             }
-            fpu_free_reg(dyn, dyn->lsx.ssecache[i].reg);
-            dyn->lsx.ssecache[i].v = -1;
         }
     if (old != -1) {
         MESSAGE(LOG_DUMP, "\t------ Purge XMM0..7 Cache\n");
@@ -976,40 +996,237 @@ static void sse_reflectcache(dynarec_la64_t* dyn, int ninst, int s1)
         }
 }
 
+// AVX helpers
+// get lasx register for a SSE reg, create the entry if needed
+int avx_get_reg(dynarec_la64_t* dyn, int ninst, int s1, int a, int forwrite, int width)
+{
+    if (dyn->lsx.avxcache[a].v != -1) {
+        if (forwrite) {
+            dyn->lsx.avxcache[a].write = 1; // update only if forwrite
+            dyn->lsx.lsxcache[dyn->lsx.avxcache[a].reg].t = LSX_CACHE_YMMW;
+        }
+        if (width == LSX_AVX_WIDTH_128) {
+            dyn->lsx.avxcache[a].width = LSX_AVX_WIDTH_128;
+            if(forwrite) dyn->lsx.avxcache[a].zero_upper = 1;
+        } else {
+            // if width changed to 256, and vzeroup ==1, means need zero-fill upper 128bits now.
+            if (dyn->lsx.avxcache[a].zero_upper == 1) {
+                dyn->lsx.avxcache[a].zero_upper = 0;
+                XVXOR_V(SCRATCH, SCRATCH, SCRATCH);
+                XVPERMI_Q(dyn->lsx.avxcache[a].reg, SCRATCH, 0b00000010);
+            }
+            dyn->lsx.avxcache[a].width = LSX_AVX_WIDTH_256;
+        }
+
+        return dyn->lsx.avxcache[a].reg;
+    }
+
+    // migrate from sse to avx
+    if (dyn->lsx.ssecache[a].v != -1) {
+        // release SSE reg cache
+        fpu_free_reg(dyn, dyn->lsx.ssecache[a].reg);
+        dyn->lsx.ssecache[a].v = -1;
+    }
+
+    // new reg
+    dyn->lsx.avxcache[a].reg = fpu_get_reg_ymm(dyn, forwrite ? LSX_CACHE_YMMW : LSX_CACHE_YMMR, a);
+    int ret = dyn->lsx.avxcache[a].reg;
+    dyn->lsx.avxcache[a].write = forwrite;
+    dyn->lsx.avxcache[a].width = width;
+    if (width == LSX_AVX_WIDTH_128) {
+        if(forwrite) dyn->lsx.avxcache[a].zero_upper = 1;
+        VLD(ret, xEmu, offsetof(x64emu_t, xmm[a]));
+    } else {
+        VLD(ret, xEmu, offsetof(x64emu_t, xmm[a]));
+        VLD(SCRATCH, xEmu, offsetof(x64emu_t, ymm[a]));
+        XVPERMI_Q(ret, SCRATCH, XVPERMI_IMM_4_0(0, 2));
+        dyn->lsx.avxcache[a].zero_upper = 0;
+    }
+    return ret;
+}
+
+int avx_get_reg_empty(dynarec_la64_t* dyn, int ninst, int s1, int a, int width)
+{
+    if (dyn->lsx.avxcache[a].v != -1) {
+        dyn->lsx.avxcache[a].write = 1;
+        dyn->lsx.lsxcache[dyn->lsx.avxcache[a].reg].t = LSX_CACHE_YMMW;
+        if (width == LSX_AVX_WIDTH_128) {
+            dyn->lsx.avxcache[a].width = LSX_AVX_WIDTH_128;
+            dyn->lsx.avxcache[a].zero_upper = 1;
+        } else {
+            dyn->lsx.avxcache[a].width = LSX_AVX_WIDTH_256;
+            dyn->lsx.avxcache[a].zero_upper = 0;
+        }
+        return dyn->lsx.avxcache[a].reg;
+    }
+    // migrate from sse to avx
+    if (dyn->lsx.ssecache[a].v != -1) {
+        // Release SSE reg cache
+        fpu_free_reg(dyn, dyn->lsx.ssecache[a].reg);
+        dyn->lsx.ssecache[a].v = -1;
+    }
+    dyn->lsx.avxcache[a].reg = fpu_get_reg_ymm(dyn, LSX_CACHE_YMMW, a);
+    dyn->lsx.avxcache[a].write = 1;
+    dyn->lsx.avxcache[a].width = width;
+    if (width == LSX_AVX_WIDTH_128){
+        dyn->lsx.avxcache[a].zero_upper = 1;
+    } else {
+        dyn->lsx.avxcache[a].zero_upper = 0;
+    }
+    return dyn->lsx.avxcache[a].reg;
+}
+
+void avx_reflect_reg_upper128(dynarec_la64_t* dyn, int ninst, int a, int forwrite)
+{
+    if (dyn->lsx.avxcache[a].v == -1 || forwrite == 0)
+        return;
+    if (dyn->lsx.lsxcache[dyn->lsx.avxcache[a].reg].t == LSX_CACHE_YMMW) {
+        if (dyn->lsx.avxcache[a].zero_upper == 1) {
+            XVXOR_V(SCRATCH, SCRATCH, SCRATCH);
+        } else {
+            XVPERMI_Q(SCRATCH, dyn->lsx.avxcache[a].reg, XVPERMI_IMM_4_0(0, 1));
+        }
+        VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[a]));
+    }
+    dyn->lsx.avxcache[a].zero_upper = 0;
+    dyn->lsx.avxcache[a].v = -1;
+    return;
+}
+
+void avx_forget_reg(dynarec_la64_t* dyn, int ninst, int a)
+{
+    if (dyn->lsx.avxcache[a].v == -1)
+        return;
+    if (dyn->lsx.lsxcache[dyn->lsx.avxcache[a].reg].t == LSX_CACHE_YMMW) {
+        VST(dyn->lsx.avxcache[a].reg, xEmu, offsetof(x64emu_t, xmm[a]));
+        if (dyn->lsx.avxcache[a].zero_upper == 1) {
+            XVXOR_V(SCRATCH, SCRATCH, SCRATCH);
+        } else {
+            XVPERMI_Q(SCRATCH, dyn->lsx.avxcache[a].reg, XVPERMI_IMM_4_0(0, 1));
+        }
+        VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[a]));
+    }
+    fpu_free_reg(dyn, dyn->lsx.avxcache[a].reg);
+    dyn->lsx.avxcache[a].zero_upper = 0;
+    dyn->lsx.avxcache[a].v = -1;
+    return;
+}
+
+void avx_reflect_reg(dynarec_la64_t* dyn, int ninst, int a)
+{
+    if (dyn->lsx.avxcache[a].v == -1)
+        return;
+    if (dyn->lsx.lsxcache[dyn->lsx.avxcache[a].reg].t == LSX_CACHE_YMMW) {
+        VST(dyn->lsx.avxcache[a].reg, xEmu, offsetof(x64emu_t, xmm[a]));
+        if (dyn->lsx.avxcache[a].zero_upper == 1) {
+            XVXOR_V(SCRATCH, SCRATCH, SCRATCH);
+            XVPERMI_Q(dyn->lsx.avxcache[a].reg, SCRATCH, 0b00000010);
+        } else {
+            XVPERMI_Q(SCRATCH, dyn->lsx.avxcache[a].reg, XVPERMI_IMM_4_0(0, 1));
+        }
+        VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[a]));
+        dyn->lsx.avxcache[a].zero_upper = 0;
+    }
+}
+
+// purge the AVX cache only
+static void avx_purgecache(dynarec_la64_t* dyn, int ninst, int next, int s1)
+{
+    int old = -1;
+    for (int i = 0; i < 16; ++i)
+        if (dyn->lsx.avxcache[i].v != -1) {
+            if (dyn->lsx.avxcache[i].write) {
+                if (old == -1) {
+                    MESSAGE(LOG_DUMP, "\tPurge %sAVX Cache ------\n", next ? "locally " : "");
+                    ++old;
+                }
+                if (dyn->lsx.lsxcache[dyn->lsx.avxcache[i].reg].t == LSX_CACHE_YMMW) {
+                    VST(dyn->lsx.avxcache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+                    if (dyn->lsx.avxcache[i].zero_upper == 1) {
+                        XVXOR_V(SCRATCH, SCRATCH, SCRATCH);
+                    } else {
+                        XVPERMI_Q(SCRATCH, dyn->lsx.avxcache[i].reg, XVPERMI_IMM_4_0(0, 1));
+                    }
+                    VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[i]));
+                }
+            }
+            if (!next) {
+                fpu_free_reg(dyn, dyn->lsx.avxcache[i].reg);
+                dyn->lsx.avxcache[i].v = -1;
+            }
+        }
+    if (old != -1) {
+        MESSAGE(LOG_DUMP, "\t------ Purge AVX Cache\n");
+    }
+}
+
+static void avx_reflectcache(dynarec_la64_t* dyn, int ninst, int s1)
+{
+    for (int i = 0; i < 16; ++i) {
+        if (dyn->lsx.avxcache[i].v != -1 && dyn->lsx.avxcache[i].write) {
+            if (dyn->lsx.lsxcache[dyn->lsx.avxcache[i].reg].t == LSX_CACHE_YMMW) {
+                avx_reflect_reg(dyn, ninst, i);
+            }
+        }
+    }
+}
+
 void fpu_pushcache(dynarec_la64_t* dyn, int ninst, int s1, int not07)
 {
     int start = not07 ? 8 : 0;
-    // only SSE regs needs to be push back to xEmu (needs to be "write")
     int n = 0;
-    for (int i = start; i < 16; i++)
+
+    for (int i = start; i < 16; i++) {
         if ((dyn->lsx.ssecache[i].v != -1) && (dyn->lsx.ssecache[i].write))
             ++n;
-    if (!n)
-        return;
-    MESSAGE(LOG_DUMP, "\tPush XMM Cache (%d)------\n", n);
-    for (int i = start; i < 16; ++i)
-        if ((dyn->lsx.ssecache[i].v != -1) && (dyn->lsx.ssecache[i].write)) {
-            VST(dyn->lsx.ssecache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+        if ((dyn->lsx.avxcache[i].v != -1) && (dyn->lsx.avxcache[i].write))
+            ++n;
+    }
+
+    if (n) {
+        MESSAGE(LOG_DUMP, "\tPush XMM/YMM Cache (%d)------\n", n);
+        for (int i = start; i < 16; ++i) {
+            if ((dyn->lsx.ssecache[i].v != -1) && (dyn->lsx.ssecache[i].write)) {
+                VST(dyn->lsx.ssecache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+            }
+            if ((dyn->lsx.avxcache[i].v != -1) && (dyn->lsx.avxcache[i].write)) {
+                    VST(dyn->lsx.avxcache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+                    if (dyn->lsx.avxcache[i].zero_upper == 0) {
+                        XVPERMI_Q(SCRATCH, dyn->lsx.avxcache[i].reg, XVPERMI_IMM_4_0(0, 1));
+                        VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[i]));
+                    }
+            }
         }
-    MESSAGE(LOG_DUMP, "\t------- Push XMM Cache (%d)\n", n);
+        MESSAGE(LOG_DUMP, "\t------- Pushed XMM/YMM Cache (%d)\n", n);
+    }
 }
 
 void fpu_popcache(dynarec_la64_t* dyn, int ninst, int s1, int not07)
 {
     int start = not07 ? 8 : 0;
-    // only SSE regs needs to be pop back from xEmu (don't need to be "write" this time)
     int n = 0;
-    for (int i = start; i < 16; i++)
-        if (dyn->lsx.ssecache[i].v != -1)
+
+    for (int i = start; i < 16; i++) {
+        if (dyn->lsx.ssecache[i].v != -1 || dyn->lsx.avxcache[i].v != -1)
             ++n;
-    if (!n)
-        return;
-    MESSAGE(LOG_DUMP, "\tPop XMM Cache (%d)------\n", n);
-    for (int i = start; i < 16; ++i)
-        if (dyn->lsx.ssecache[i].v != -1) {
-            VLD(dyn->lsx.ssecache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+    }
+
+    if (n) {
+        MESSAGE(LOG_DUMP, "\tPop XMM/YMM Cache (%d)------\n", n);
+        for (int i = start; i < 16; ++i) {
+            if (dyn->lsx.ssecache[i].v != -1) {
+                VLD(dyn->lsx.ssecache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+            }
+            if (dyn->lsx.avxcache[i].v != -1) {
+                VLD(dyn->lsx.avxcache[i].reg, xEmu, offsetof(x64emu_t, xmm[i]));
+                if (dyn->lsx.avxcache[i].zero_upper == 0) {
+                    VLD(SCRATCH, xEmu, offsetof(x64emu_t, ymm[i]));
+                    XVPERMI_Q(dyn->lsx.avxcache[i].reg, SCRATCH, XVPERMI_IMM_4_0(0, 2));
+                }
+            }
         }
-    MESSAGE(LOG_DUMP, "\t------- Pop XMM Cache (%d)\n", n);
+        MESSAGE(LOG_DUMP, "\t------- Pop XMM/YMM Cache (%d)\n", n);
+    }
 }
 
 void fpu_purgecache(dynarec_la64_t* dyn, int ninst, int next, int s1, int s2, int s3)
@@ -1017,6 +1234,7 @@ void fpu_purgecache(dynarec_la64_t* dyn, int ninst, int next, int s1, int s2, in
     x87_purgecache(dyn, ninst, next, s1, s2, s3);
     mmx_purgecache(dyn, ninst, next, s1);
     sse_purgecache(dyn, ninst, next, s1);
+    avx_purgecache(dyn, ninst, next, s1);
     if (!next)
         fpu_reset_reg(dyn);
 }
@@ -1026,6 +1244,7 @@ void fpu_reflectcache(dynarec_la64_t* dyn, int ninst, int s1, int s2, int s3)
     // TODO: x87_reflectcache(dyn, ninst, s1, s2, s3);
     mmx_reflectcache(dyn, ninst, s1);
     sse_reflectcache(dyn, ninst, s1);
+    avx_reflectcache(dyn, ninst, s1);
 }
 
 void fpu_unreflectcache(dynarec_la64_t* dyn, int ninst, int s1, int s2, int s3)
@@ -1124,6 +1343,14 @@ static int findCacheSlot(dynarec_la64_t* dyn, int ninst, int t, int n, lsxcache_
                     if (t == LSX_CACHE_XMMR)
                         return i;
                     break;
+                case LSX_CACHE_YMMR:
+                    if (t == LSX_CACHE_YMMW)
+                        return i;
+                    break;
+                case LSX_CACHE_YMMW:
+                    if (t == LSX_CACHE_YMMR)
+                        return i;
+                    break;
             }
         }
     }
@@ -1139,15 +1366,25 @@ static void swapCache(dynarec_la64_t* dyn, int ninst, int i, int j, lsxcache_t*
         quad = 1;
     if (cache->lsxcache[j].t == LSX_CACHE_XMMR || cache->lsxcache[j].t == LSX_CACHE_XMMW)
         quad = 1;
+    if (cache->lsxcache[i].t == LSX_CACHE_YMMR || cache->lsxcache[i].t == LSX_CACHE_YMMW)
+        quad = 2;
+    if (cache->lsxcache[j].t == LSX_CACHE_YMMR || cache->lsxcache[j].t == LSX_CACHE_YMMW)
+        quad = 2;
 
     if (!cache->lsxcache[i].v) {
         // a mov is enough, no need to swap
         MESSAGE(LOG_DUMP, "\t  - Moving %d <- %d\n", i, j);
-        if (quad) {
-            VOR_V(i, j, j);
-        } else {
-            VXOR_V(i, i, i);
-            VEXTRINS_D(i, j, 0);
+        switch (quad) {
+            case 2:
+                XVOR_V(i, j, j);
+                break;
+            case 1:
+                VOR_V(i, j, j);
+                break;
+            default:
+                VXOR_V(i, i, i);
+                VEXTRINS_D(i, j, 0);
+                break;
         }
         cache->lsxcache[i].v = cache->lsxcache[j].v;
         cache->lsxcache[j].v = 0;
@@ -1158,17 +1395,25 @@ static void swapCache(dynarec_la64_t* dyn, int ninst, int i, int j, lsxcache_t*
     MESSAGE(LOG_DUMP, "\t  - Swapping %d <-> %d\n", i, j);
     // There is no VSWP in Arm64 NEON to swap 2 register contents!
     // so use a scratch...
-    if (quad) {
-        VOR_V(SCRATCH, i, i);
-        VOR_V(i, j, j);
-        VOR_V(j, SCRATCH, SCRATCH);
-    } else {
-        VXOR_V(SCRATCH, SCRATCH, SCRATCH);
-        VEXTRINS_D(SCRATCH, i, 0);
-        VXOR_V(i, i, i);
-        VEXTRINS_D(i, j, 0);
-        VXOR_V(j, j, j);
-        VEXTRINS_D(j, SCRATCH, 0);
+    switch (quad) {
+        case 2:
+            XVOR_V(SCRATCH, i, i);
+            XVOR_V(i, j, j);
+            XVOR_V(j, SCRATCH, SCRATCH);
+            break;
+        case 1:
+            VOR_V(SCRATCH, i, i);
+            VOR_V(i, j, j);
+            VOR_V(j, SCRATCH, SCRATCH);
+            break;
+        default:
+            VXOR_V(SCRATCH, SCRATCH, SCRATCH);
+            VEXTRINS_D(SCRATCH, i, 0);
+            VXOR_V(i, i, i);
+            VEXTRINS_D(i, j, 0);
+            VXOR_V(j, j, j);
+            VEXTRINS_D(j, SCRATCH, 0);
+            break;
     }
     tmp.v = cache->lsxcache[i].v;
     cache->lsxcache[i].v = cache->lsxcache[j].v;
@@ -1181,21 +1426,38 @@ static void loadCache(dynarec_la64_t* dyn, int ninst, int stack_cnt, int s1, int
         int quad = 0;
         if (t == LSX_CACHE_XMMR || t == LSX_CACHE_XMMW)
             quad = 1;
+        if (t == LSX_CACHE_YMMR || t == LSX_CACHE_YMMW)
+            quad = 2;
         if (cache->lsxcache[i].t == LSX_CACHE_XMMR || cache->lsxcache[i].t == LSX_CACHE_XMMW)
             quad = 1;
+        if (cache->lsxcache[i].t == LSX_CACHE_YMMR || cache->lsxcache[i].t == LSX_CACHE_YMMW)
+            quad = 2;
         int j = i + 1;
         while (cache->lsxcache[j].v)
             ++j;
         MESSAGE(LOG_DUMP, "\t  - Moving away %d\n", i);
-        if (quad) {
-            VOR_V(j, i, i);
-        } else {
-            VXOR_V(j, j, j);
-            VEXTRINS_D(j, i, 0);
+        switch (quad) {
+            case 2:
+                XVOR_V(j, i, i);
+                break;
+            case 1:
+                VOR_V(j, i, i);
+                break;
+            default:
+                VXOR_V(j, j, j);
+                VEXTRINS_D(j, i, 0);
+                break;
         }
         cache->lsxcache[j].v = cache->lsxcache[i].v;
     }
     switch (t) {
+        case LSX_CACHE_YMMR:
+        case LSX_CACHE_YMMW:
+            MESSAGE(LOG_DUMP, "\t  - Loading %s\n", getCacheName(t, n));
+            VLD(i, xEmu, offsetof(x64emu_t, xmm[n]));
+            VLD(SCRATCH, xEmu, offsetof(x64emu_t, ymm[n]));
+            XVPERMI_Q(i, SCRATCH, XVPERMI_IMM_4_0(0, 2));
+            break;
         case LSX_CACHE_XMMR:
         case LSX_CACHE_XMMW:
             MESSAGE(LOG_DUMP, "\t  - Loading %s\n", getCacheName(t, n));
@@ -1227,12 +1489,19 @@ static void unloadCache(dynarec_la64_t* dyn, int ninst, int stack_cnt, int s1, i
 {
     switch (t) {
         case LSX_CACHE_XMMR:
+        case LSX_CACHE_YMMR:
             MESSAGE(LOG_DUMP, "\t  - ignoring %s\n", getCacheName(t, n));
             break;
         case LSX_CACHE_XMMW:
             MESSAGE(LOG_DUMP, "\t  - Unloading %s\n", getCacheName(t, n));
             VST(i, xEmu, offsetof(x64emu_t, xmm[n]));
             break;
+        case LSX_CACHE_YMMW:
+            MESSAGE(LOG_DUMP, "\t  - Unloading %s\n", getCacheName(t, n));
+            XVPERMI_Q(SCRATCH, i, XVPERMI_IMM_4_0(0, 1));
+            VST(i, xEmu, offsetof(x64emu_t, xmm[n]));
+            VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[n]));
+            break;
         case LSX_CACHE_MM:
             MESSAGE(LOG_DUMP, "\t  - Unloading %s\n", getCacheName(t, n));
             FST_D(i, xEmu, offsetof(x64emu_t, mmx[n]));
@@ -1302,6 +1571,11 @@ static void fpuCacheTransform(dynarec_la64_t* dyn, int ninst, int s1, int s2, in
     // unload every unneeded cache
     // check SSE first, than MMX, in order, for optimization issue
     for (int i = 0; i < 16; ++i) {
+        int j = findCacheSlot(dyn, ninst, LSX_CACHE_YMMW, i, &cache);
+        if (j >= 0 && findCacheSlot(dyn, ninst, LSX_CACHE_YMMW, i, &cache_i2) == -1)
+            unloadCache(dyn, ninst, stack_cnt, s1, s2, s3, &s1_val, &s2_val, &s3_top, &cache, j, cache.lsxcache[j].t, cache.lsxcache[j].n);
+    }
+    for (int i = 0; i < 16; ++i) {
         int j = findCacheSlot(dyn, ninst, LSX_CACHE_XMMW, i, &cache);
         if (j >= 0 && findCacheSlot(dyn, ninst, LSX_CACHE_XMMW, i, &cache_i2) == -1)
             unloadCache(dyn, ninst, stack_cnt, s1, s2, s3, &s1_val, &s2_val, &s3_top, &cache, j, cache.lsxcache[j].t, cache.lsxcache[j].n);
@@ -1356,6 +1630,15 @@ static void fpuCacheTransform(dynarec_la64_t* dyn, int ninst, int s1, int s2, in
                     cache.lsxcache[i].t = LSX_CACHE_ST_D;
                 } else if (cache.lsxcache[i].t == LSX_CACHE_XMMR && cache_i2.lsxcache[i].t == LSX_CACHE_XMMW) {
                     cache.lsxcache[i].t = LSX_CACHE_XMMW;
+                } else if (cache.lsxcache[i].t == LSX_CACHE_YMMR && cache_i2.lsxcache[i].t == LSX_CACHE_YMMW) {
+                    cache.lsxcache[i].t = LSX_CACHE_YMMW;
+                } else if (cache.lsxcache[i].t == LSX_CACHE_YMMW && cache_i2.lsxcache[i].t == LSX_CACHE_YMMR) {
+                    // refresh cache...
+                    MESSAGE(LOG_DUMP, "\t  - Refreh %s\n", getCacheName(cache.lsxcache[i].t, cache.lsxcache[i].n));
+                    XVPERMI_Q(SCRATCH, i, XVPERMI_IMM_4_0(0, 1));
+                    VST(i, xEmu, offsetof(x64emu_t, xmm[cache.lsxcache[i].n]));
+                    VST(SCRATCH, xEmu, offsetof(x64emu_t, ymm[cache.lsxcache[i].n]));
+                    cache.lsxcache[i].t = LSX_CACHE_YMMR;
                 } else if (cache.lsxcache[i].t == LSX_CACHE_XMMW && cache_i2.lsxcache[i].t == LSX_CACHE_XMMR) {
                     // refresh cache...
                     MESSAGE(LOG_DUMP, "\t  - Refreh %s\n", getCacheName(cache.lsxcache[i].t, cache.lsxcache[i].n));
diff --git a/src/dynarec/la64/dynarec_la64_helper.h b/src/dynarec/la64/dynarec_la64_helper.h
index 30774ca3..6f37c293 100644
--- a/src/dynarec/la64/dynarec_la64_helper.h
+++ b/src/dynarec/la64/dynarec_la64_helper.h
@@ -326,6 +326,7 @@
     }
 
 #define VEXTRINS_IMM_4_0(n, m) ((n & 0xf) << 4 | (m & 0xf))
+#define XVPERMI_IMM_4_0(n, m) ((n & 0xf) << 4 | (m & 0xf))
 
 // Get GX as a quad (might use x1)
 #define GETGX(a, w)                             \
@@ -433,6 +434,211 @@
         BSTRINS_D(wback, ed, wb2 + 7, wb2); \
     }
 
+#define YMM_UNMARK_UPPER_ZERO(a)                                  \
+    do {                                         \
+        dyn->lsx.avxcache[a].zero_upper = 0;     \
+    } while (0)
+
+// AVX helpers
+// Get VX (might use x1)
+#define GETVYx(a, w) \
+    a = avx_get_reg(dyn, ninst, x1, vex.v, w, LSX_AVX_WIDTH_128)
+
+#define GETVYy(a, w) \
+    a = avx_get_reg(dyn, ninst, x1, vex.v, w, LSX_AVX_WIDTH_256)
+
+// Get an empty VX (use x1)
+#define GETVYx_empty(a) \
+    a = avx_get_reg_empty(dyn, ninst, x1, vex.v, LSX_AVX_WIDTH_128)
+
+#define GETVYy_empty(a) \
+    a = avx_get_reg_empty(dyn, ninst, x1, vex.v, LSX_AVX_WIDTH_256)
+
+// Get GX as a quad (might use x1)
+#define GETGYx(a, w)                            \
+    gd = ((nextop & 0x38) >> 3) + (rex.r << 3); \
+    a = avx_get_reg(dyn, ninst, x1, gd, w, LSX_AVX_WIDTH_128)
+
+#define GETGYy(a, w)                            \
+    gd = ((nextop & 0x38) >> 3) + (rex.r << 3); \
+    a = avx_get_reg(dyn, ninst, x1, gd, w, LSX_AVX_WIDTH_256)
+
+#define GETGYx_empty(a)                         \
+    gd = ((nextop & 0x38) >> 3) + (rex.r << 3); \
+    a = avx_get_reg_empty(dyn, ninst, x1, gd, LSX_AVX_WIDTH_128)
+
+#define GETGYy_empty(a)                         \
+    gd = ((nextop & 0x38) >> 3) + (rex.r << 3); \
+    a = avx_get_reg_empty(dyn, ninst, x1, gd, LSX_AVX_WIDTH_256)
+
+// Get EY as a quad, (x1 is used)
+#define GETEYx(a, w, D)                                                                      \
+    if (MODREG) {                                                                            \
+        a = avx_get_reg(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), w, LSX_AVX_WIDTH_128);  \
+    } else {                                                                                 \
+        SMREAD();                                                                            \
+        addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, D); \
+        a = fpu_get_scratch(dyn);                                                            \
+        VLD(a, ed, fixedaddress);                                                            \
+    }
+
+#define GETEYy(a, w, D)                                                                      \
+    if (MODREG) {                                                                            \
+        a = avx_get_reg(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), w, LSX_AVX_WIDTH_256);  \
+    } else {                                                                                 \
+        SMREAD();                                                                            \
+        addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, D); \
+        a = fpu_get_scratch(dyn);                                                            \
+        XVLD(a, ed, fixedaddress);                                                           \
+    }
+
+#define GETEYx_empty(a, D)                                                                     \
+    if (MODREG) {                                                                              \
+        a = avx_get_reg_empty(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), LSX_AVX_WIDTH_128); \
+    } else {                                                                                   \
+        SMREAD();                                                                              \
+        addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, D);   \
+        a = fpu_get_scratch(dyn);                                                              \
+    }
+
+#define GETEYy_empty(a, D)                                                                     \
+    if (MODREG) {                                                                              \
+        a = avx_get_reg_empty(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), LSX_AVX_WIDTH_256); \
+    } else {                                                                                   \
+        SMREAD();                                                                              \
+        addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, D);   \
+        a = fpu_get_scratch(dyn);                                                              \
+    }
+
+// Get EY as 32bits , (x1 is used)
+#define GETEYSS(a, w, D)                                                                     \
+    if (MODREG) {                                                                            \
+        a = avx_get_reg(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), w, LSX_AVX_WIDTH_128);  \
+    } else {                                                                                 \
+        SMREAD();                                                                            \
+        addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, D); \
+        a = fpu_get_scratch(dyn);                                                            \
+        FLD_S(a, ed, fixedaddress);                                                          \
+    }
+
+#define PUTEYSS(a)                  \
+    if (!MODREG) {                  \
+        FST_S(a, ed, fixedaddress); \
+        SMWRITE2();                 \
+    }
+
+// Get EY as 32bits , (x1 is used)
+#define GETEYSD(a, w, D)                                                                     \
+    if (MODREG) {                                                                            \
+        a = avx_get_reg(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), w, LSX_AVX_WIDTH_128);  \
+    } else {                                                                                 \
+        SMREAD();                                                                            \
+        addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, D); \
+        a = fpu_get_scratch(dyn);                                                            \
+        FLD_D(a, ed, fixedaddress);                                                          \
+    }
+
+#define PUTEYSD(a)                  \
+    if (!MODREG) {                  \
+        FST_D(a, ed, fixedaddress); \
+        SMWRITE2();                 \
+    }
+
+#define GETGYxy(a, w) \
+    if (vex.l) {      \
+        GETGYy(a, w); \
+    } else {          \
+        GETGYx(a, w); \
+    }
+
+#define GETGYxy_empty(a) \
+    if (vex.l) {         \
+        GETGYy_empty(a); \
+    } else {             \
+        GETGYx_empty(a); \
+    }
+
+#define GETVYxy(a, w) \
+    if (vex.l) {      \
+        GETVYy(a, w); \
+    } else {          \
+        GETVYx(a, w); \
+    }
+
+#define GETVYxy_empty(a) \
+    if (vex.l) {         \
+        GETVYy_empty(a); \
+    } else {             \
+        GETVYx_empty(a); \
+    }
+
+#define GETEYxy(a, w, D) \
+    if (vex.l) {         \
+        GETEYy(a, w, D); \
+    } else {             \
+        GETEYx(a, w, D); \
+    }
+
+#define GETEYxy_empty(a, D) \
+    if (vex.l) {            \
+        GETEYy_empty(a, D); \
+    } else {                \
+        GETEYx_empty(a, D); \
+    }
+
+// Put Back EY if it was a memory and not an emm register
+#define PUTEYy(a)                  \
+    if (!MODREG) {                 \
+        XVST(a, ed, fixedaddress); \
+        SMWRITE2();                \
+    }
+
+#define PUTEYx(a)                 \
+    if (!MODREG) {                \
+        VST(a, ed, fixedaddress); \
+        SMWRITE2();               \
+    }
+
+#define PUTEYxy(a) \
+    if (vex.l) {   \
+        PUTEYy(a); \
+    } else {       \
+        PUTEYx(a); \
+    }
+
+// Get empty GY, and non-written VY and EY
+#define GETGY_empty_VYEY_xy(gx, vx, ex, D)  \
+    GETVYxy(vx, 0);                         \
+    GETEYxy(ex, 0, D);                      \
+    GETGYxy_empty(gx);
+
+// Get empty GY, and non-written EY
+#define GETGY_empty_EY_xy(gx, ex, D)  \
+    GETEYxy(ex, 0, D);                \
+    GETGYxy_empty(gx);
+
+// Get writable GY, and non-written VY and EY
+#define GETGY_VYEY_xy(gx, vx, ex, D)  \
+    GETVYxy(vx, 0);                   \
+    GETEYxy(ex, 0, D);                \
+    GETGYxy(gx, 1);
+
+// Get writable GY, and non-written EY
+#define GETGY_EY_xy(gx, ex, D)  \
+    GETEYxy(ex, 0, D);          \
+    GETGYxy(gx, 1);
+
+// Get writable EY, and non-written VY and GY
+#define GETEY_VYGY_xy(gx, vx, ex, D)  \
+    GETVYxy(vx, 0);                   \
+    GETGYxy(gx, 0);                   \
+    GETEYxy(ex, 1, D);
+
+// Get writable EY, and non-written GY
+#define GETEY_GY_xy(ex, gx, D)  \
+    GETGYxy(gx, 0);             \
+    GETEYxy(ex, 1, D);
+
 // Get direction with size Z and based of F_DF flag, on register r ready for load/store fetching
 // using s as scratch.
 // F_DF is not in LBT4.eflags, don't worry
@@ -876,19 +1082,26 @@ void* la64_next(x64emu_t* emu, uintptr_t addr);
 
 #define native_pass STEPNAME(native_pass)
 
-#define dynarec64_00     STEPNAME(dynarec64_00)
-#define dynarec64_0F     STEPNAME(dynarec64_0F)
-#define dynarec64_64     STEPNAME(dynarec64_64)
-#define dynarec64_66     STEPNAME(dynarec64_66)
-#define dynarec64_6664   STEPNAME(dynarec64_6664)
-#define dynarec64_67     STEPNAME(dynarec64_67)
-#define dynarec64_F30F   STEPNAME(dynarec64_F30F)
-#define dynarec64_660F   STEPNAME(dynarec64_660F)
-#define dynarec64_66F0   STEPNAME(dynarec64_66F0)
-#define dynarec64_66F20F STEPNAME(dynarec64_66F20F)
-#define dynarec64_66F30F STEPNAME(dynarec64_66F30F)
-#define dynarec64_F0     STEPNAME(dynarec64_F0)
-#define dynarec64_F20F   STEPNAME(dynarec64_F20F)
+#define dynarec64_00          STEPNAME(dynarec64_00)
+#define dynarec64_0F          STEPNAME(dynarec64_0F)
+#define dynarec64_64          STEPNAME(dynarec64_64)
+#define dynarec64_66          STEPNAME(dynarec64_66)
+#define dynarec64_6664        STEPNAME(dynarec64_6664)
+#define dynarec64_67          STEPNAME(dynarec64_67)
+#define dynarec64_F30F        STEPNAME(dynarec64_F30F)
+#define dynarec64_660F        STEPNAME(dynarec64_660F)
+#define dynarec64_66F0        STEPNAME(dynarec64_66F0)
+#define dynarec64_66F20F      STEPNAME(dynarec64_66F20F)
+#define dynarec64_66F30F      STEPNAME(dynarec64_66F30F)
+#define dynarec64_F0          STEPNAME(dynarec64_F0)
+#define dynarec64_F20F        STEPNAME(dynarec64_F20F)
+#define dynarec64_AVX         STEPNAME(dynarec64_AVX)
+#define dynarec64_AVX_0F      STEPNAME(dynarec64_AVX_0F)
+#define dynarec64_AVX_66_0F   STEPNAME(dynarec64_AVX_66_0F)
+#define dynarec64_AVX_66_0F38 STEPNAME(dynarec64_AVX_66_0F38)
+#define dynarec64_AVX_66_0F3A STEPNAME(dynarec64_AVX_66_0F3A)
+#define dynarec64_AVX_F2_0F   STEPNAME(dynarec64_AVX_F3_0F)
+#define dynarec64_AVX_F3_0F   STEPNAME(dynarec64_AVX_F3_0F)
 
 #define geted               STEPNAME(geted)
 #define geted32             STEPNAME(geted32)
@@ -987,6 +1200,14 @@ void* la64_next(x64emu_t* emu, uintptr_t addr);
 #define sse_forget_reg    STEPNAME(sse_forget_reg)
 #define sse_reflect_reg   STEPNAME(sse_reflect_reg)
 
+#define avx_get_reg            STEPNAME(avx_get_reg)
+#define avx_get_reg_empty      STEPNAME(avx_get_reg_empty)
+#define avx_forget_reg         STEPNAME(sse_forget_reg)
+#define avx_reflect_reg        STEPNAME(avx_reflect_reg)
+#define avx_purgecache         STEPNAME(avx_purgecache)
+#define avx_reflect_reg_upper128 STEPNAME(avx_reflect_reg_upper128)
+
+
 #define fpu_pushcache       STEPNAME(fpu_pushcache)
 #define fpu_popcache        STEPNAME(fpu_popcache)
 #define fpu_reset_cache     STEPNAME(fpu_reset_cache)
@@ -1129,6 +1350,17 @@ int mmx_get_reg(dynarec_la64_t* dyn, int ninst, int s1, int s2, int s3, int a);
 int mmx_get_reg_empty(dynarec_la64_t* dyn, int ninst, int s1, int s2, int s3, int a);
 
 
+// AVX helpers
+// get lasx register for a AVX reg, create the entry if needed
+int avx_get_reg(dynarec_la64_t* dyn, int ninst, int s1, int a, int forwrite, int width);
+// get lasx register for an AVX reg, but don't try to synch it if it needed to be created
+int avx_get_reg_empty(dynarec_la64_t* dyn, int ninst, int s1, int a, int width);
+// forget float register for a AVX reg, create the entry if needed
+void avx_forget_reg(dynarec_la64_t* dyn, int ninst, int a);
+// Push current value to the cache
+void avx_reflect_reg(dynarec_la64_t* dyn, int ninst, int a);
+void avx_reflect_reg_upper128(dynarec_la64_t* dyn, int ninst, int a, int forwrite);
+
 void CacheTransform(dynarec_la64_t* dyn, int ninst, int cacheupd, int s1, int s2, int s3);
 
 void la64_move64(dynarec_la64_t* dyn, int ninst, int reg, int64_t val);
@@ -1153,6 +1385,14 @@ uintptr_t dynarec64_66F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, in
 uintptr_t dynarec64_66F30F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog);
 uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog);
+uintptr_t dynarec64_AVX(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog);
+uintptr_t dynarec64_AVX_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog);
+uintptr_t dynarec64_AVX_66_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog);
+uintptr_t dynarec64_AVX_66_0F38(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog);
+uintptr_t dynarec64_AVX_66_0F3A(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog);
+uintptr_t dynarec64_AVX_F2_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog);
+uintptr_t dynarec64_AVX_F3_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog);
+
 
 #if STEP < 3
 #define PASS3(A)
@@ -1299,6 +1539,6 @@ uintptr_t dynarec64_F20F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int
         }                                  \
     } while (0)
 
-#define PURGE_YMM() /* TODO */
+#define PURGE_YMM()
 
 #endif //__DYNAREC_LA64_HELPER_H__
diff --git a/src/dynarec/la64/dynarec_la64_private.h b/src/dynarec/la64/dynarec_la64_private.h
index 0275218b..8f433fe5 100644
--- a/src/dynarec/la64/dynarec_la64_private.h
+++ b/src/dynarec/la64/dynarec_la64_private.h
@@ -16,7 +16,12 @@ typedef struct instsize_s instsize_t;
 #define LSX_CACHE_MM     4
 #define LSX_CACHE_XMMW   5
 #define LSX_CACHE_XMMR   6
-#define LSX_CACHE_SCR    7
+#define LSX_CACHE_YMMW   7
+#define LSX_CACHE_YMMR   8
+#define LSX_CACHE_SCR    9
+
+#define LSX_AVX_WIDTH_128 0
+#define LSX_AVX_WIDTH_256 1
 
 typedef union lsx_cache_s {
     int8_t v;
@@ -34,6 +39,16 @@ typedef union sse_cache_s {
     };
 } sse_cache_t;
 
+typedef union avx_cache_s {
+    int8_t v;
+    struct {
+        uint8_t reg : 5;
+        uint8_t width : 1;
+        uint8_t zero_upper : 1;        
+        uint8_t write : 1;
+    };
+} avx_cache_t;
+
 typedef struct lsxcache_s {
     // LSX cache
     lsx_cache_t     lsxcache[24];
@@ -54,6 +69,7 @@ typedef struct lsxcache_s {
     int16_t         tags;           // similar to fpu_tags
     int8_t          mmxcache[8];    // cache status for the 8 MMX registers
     sse_cache_t     ssecache[16];   // cache status for the 16 SSE(2) registers
+    avx_cache_t     avxcache[16];   // cache status for the 16 SSE(2) registers
     int8_t          fpuused[24];    // all 0..24 double reg from fpu, used by x87, sse and mmx
     int8_t          x87stack;       // cache stack counter
     int8_t          mmxcount;       // number of mmx register used (not both mmx and x87 at the same time)
diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h
index 41a87db9..28dc5d63 100644
--- a/src/dynarec/la64/la64_emitter.h
+++ b/src/dynarec/la64/la64_emitter.h
@@ -1518,7 +1518,19 @@ LSX instruction starts with V, LASX instruction starts with XV.
 #define VLDREPL_B(vd, rj, imm12)     EMIT(type_2RI12(0b0011000010, imm12, rj, vd))
 #define VFCMP_S(vd, vj, vk, cond)    EMIT(type_4R(0b000011000101, cond, vk, vj, vd))
 #define VFCMP_D(vd, vj, vk, cond)    EMIT(type_4R(0b000011000110, cond, vk, vj, vd))
+#define XVFCMP_S(vd, vj, vk, cond)   EMIT(type_4R(0b000011001001, cond, vk, vj, vd))
+#define XVFCMP_D(vd, vj, vk, cond)   EMIT(type_4R(0b000011001010, cond, vk, vj, vd))
 #define VPERMI_W(vd, vj, imm8)       EMIT(type_2RI8(0b01110011111001, imm8, vj, vd))
+#define VFMADD_S(vd, vj, vk, va)     EMIT(type_4R(0b000010010001, va, vk, vj, vd))
+#define VFMSUB_S(vd, vj, vk, va)     EMIT(type_4R(0b000010010101, va, vk, vj, vd))
+#define VFNMADD_S(vd, vj, vk, va)    EMIT(type_4R(0b000010011001, va, vk, vj, vd))
+#define VFNMSUB_S(vd, vj, vk, va)    EMIT(type_4R(0b000010011101, va, vk, vj, vd))
+#define VFMADD_D(vd, vj, vk, va)     EMIT(type_4R(0b000010010010, va, vk, vj, vd))
+#define VFMSUB_D(vd, vj, vk, va)     EMIT(type_4R(0b000010010110, va, vk, vj, vd))
+#define VFNMADD_D(vd, vj, vk, va)    EMIT(type_4R(0b000010011010, va, vk, vj, vd))
+#define VFNMSUB_D(vd, vj, vk, va)    EMIT(type_4R(0b000010011110, va, vk, vj, vd))
+
+
 #define XVADD_B(vd, vj, vk)          EMIT(type_3R(0b01110100000010100, vk, vj, vd))
 #define XVADD_H(vd, vj, vk)          EMIT(type_3R(0b01110100000010101, vk, vj, vd))
 #define XVADD_W(vd, vj, vk)          EMIT(type_3R(0b01110100000010110, vk, vj, vd))
@@ -1817,6 +1829,62 @@ LSX instruction starts with V, LASX instruction starts with XV.
 #define XVBITREV_D(vd, vj, vk)       EMIT(type_3R(0b01110101000100011, vk, vj, vd))
 #define XVFRSTP_B(vd, vj, vk)        EMIT(type_3R(0b01110101001010110, vk, vj, vd))
 #define XVFRSTP_H(vd, vj, vk)        EMIT(type_3R(0b01110101001010111, vk, vj, vd))
+#define XVCLO_B(xd, xj)              EMIT(type_2R(0b0111011010011100000000, xj, xd))
+#define XVCLO_H(xd, xj)              EMIT(type_2R(0b0111011010011100000001, xj, xd))
+#define XVCLO_W(xd, xj)              EMIT(type_2R(0b0111011010011100000010, xj, xd))
+#define XVCLO_D(xd, xj)              EMIT(type_2R(0b0111011010011100000011, xj, xd))
+#define XVCLZ_B(xd, xj)              EMIT(type_2R(0b0111011010011100000100, xj, xd))
+#define XVCLZ_H(xd, xj)              EMIT(type_2R(0b0111011010011100000101, xj, xd))
+#define XVCLZ_W(xd, xj)              EMIT(type_2R(0b0111011010011100000110, xj, xd))
+#define XVCLZ_D(xd, xj)              EMIT(type_2R(0b0111011010011100000111, xj, xd))
+#define XVPCNT_B(xd, xj)             EMIT(type_2R(0b0111011010011100001000, xj, xd))
+#define XVPCNT_H(xd, xj)             EMIT(type_2R(0b0111011010011100001001, xj, xd))
+#define XVPCNT_W(xd, xj)             EMIT(type_2R(0b0111011010011100001010, xj, xd))
+#define XVPCNT_D(xd, xj)             EMIT(type_2R(0b0111011010011100001011, xj, xd))
+#define XVNEG_B(xd, xj)              EMIT(type_2R(0b0111011010011100001100, xj, xd))
+#define XVNEG_H(xd, xj)              EMIT(type_2R(0b0111011010011100001101, xj, xd))
+#define XVNEG_W(xd, xj)              EMIT(type_2R(0b0111011010011100001110, xj, xd))
+#define XVNEG_D(xd, xj)              EMIT(type_2R(0b0111011010011100001111, xj, xd))
+#define XVMSKLTZ_B(xd, xj)           EMIT(type_2R(0b0111011010011100010000, xj, xd))
+#define XVMSKLTZ_H(xd, xj)           EMIT(type_2R(0b0111011010011100010001, xj, xd))
+#define XVMSKLTZ_W(xd, xj)           EMIT(type_2R(0b0111011010011100010010, xj, xd))
+#define XVMSKLTZ_D(xd, xj)           EMIT(type_2R(0b0111011010011100010011, xj, xd))
+#define XVMSKGEZ_B(xd, xj)           EMIT(type_2R(0b0111011010011100010100, xj, xd))
+#define XVMSKNZ_B(xd, xj)            EMIT(type_2R(0b0111011010011100011000, xj, xd))
+#define XVSETEQZ_V(cd, xj)           EMIT(type_2R(0b011101101001110010011000, xj, cd & 0b111))
+#define XVSETNEZ_V(cd, xj)           EMIT(type_2R(0b011101101001110010011100, xj, cd & 0b111))
+#define XVSETANYEQZ_B(cd, xj)        EMIT(type_2R(0b011101101001110010100000, xj, cd & 0b111))
+#define XVSETANYEQZ_H(cd, xj)        EMIT(type_2R(0b011101101001110010100100, xj, cd & 0b111))
+#define XVSETANYEQZ_W(cd, xj)        EMIT(type_2R(0b011101101001110010101000, xj, cd & 0b111))
+#define XVSETANYEQZ_D(cd, xj)        EMIT(type_2R(0b011101101001110010101100, xj, cd & 0b111))
+#define XVSETALLNEZ_B(cd, xj)        EMIT(type_2R(0b011101101001110010110000, xj, cd & 0b111))
+#define XVSETALLNEZ_H(cd, xj)        EMIT(type_2R(0b011101101001110010110100, xj, cd & 0b111))
+#define XVSETALLNEZ_W(cd, xj)        EMIT(type_2R(0b011101101001110010111000, xj, cd & 0b111))
+#define XVSETALLNEZ_D(cd, xj)        EMIT(type_2R(0b011101101001110010111100, xj, cd & 0b111))
+#define XVFLOGB_S(xd, xj)            EMIT(type_2R(0b0111011010011100110001, xj, xd))
+#define XVFLOGB_D(xd, xj)            EMIT(type_2R(0b0111011010011100110010, xj, xd))
+#define XVFCLASS_S(xd, xj)           EMIT(type_2R(0b0111011010011100110101, xj, xd))
+#define XVFCLASS_D(xd, xj)           EMIT(type_2R(0b0111011010011100110110, xj, xd))
+#define XVFSQRT_S(xd, xj)            EMIT(type_2R(0b0111011010011100111001, xj, xd))
+#define XVFSQRT_D(xd, xj)            EMIT(type_2R(0b0111011010011100111010, xj, xd))
+#define XVFRECIP_S(xd, xj)           EMIT(type_2R(0b0111011010011100111101, xj, xd))
+#define XVFRECIP_D(xd, xj)           EMIT(type_2R(0b0111011010011100111110, xj, xd))
+#define XVFRSQRT_S(xd, xj)           EMIT(type_2R(0b0111011010011101000001, xj, xd))
+#define XVFRSQRT_D(xd, xj)           EMIT(type_2R(0b0111011010011101000010, xj, xd))
+#define XVFRECIPE_S(xd, xj)          EMIT(type_2R(0b0111011010011101000101, xj, xd))
+#define XVFRECIPE_D(xd, xj)          EMIT(type_2R(0b0111011010011101000110, xj, xd))
+#define XVFRSQRTE_S(xd, xj)          EMIT(type_2R(0b0111011010011101001001, xj, xd))
+#define XVFRSQRTE_D(xd, xj)          EMIT(type_2R(0b0111011010011101001010, xj, xd))
+#define XVFRINT_S(xd, xj)            EMIT(type_2R(0b0111011010011101001101, xj, xd))
+#define XVFRINT_D(xd, xj)            EMIT(type_2R(0b0111011010011101001110, xj, xd))
+#define XVFRINTRM_S(xd, xj)          EMIT(type_2R(0b0111011010011101010001, xj, xd))
+#define XVFRINTRM_D(xd, xj)          EMIT(type_2R(0b0111011010011101010010, xj, xd))
+#define XVFRINTRP_S(xd, xj)          EMIT(type_2R(0b0111011010011101010101, xj, xd))
+#define XVFRINTRP_D(xd, xj)          EMIT(type_2R(0b0111011010011101010110, xj, xd))
+#define XVFRINTRZ_S(xd, xj)          EMIT(type_2R(0b0111011010011101011001, xj, xd))
+#define XVFRINTRZ_D(xd, xj)          EMIT(type_2R(0b0111011010011101011010, xj, xd))
+#define XVFRINTRNE_S(xd, xj)         EMIT(type_2R(0b0111011010011101011101, xj, xd))
+#define XVFRINTRNE_D(xd, xj)         EMIT(type_2R(0b0111011010011101011110, xj, xd))
 #define XVFADD_S(vd, vj, vk)         EMIT(type_3R(0b01110101001100001, vk, vj, vd))
 #define XVFADD_D(vd, vj, vk)         EMIT(type_3R(0b01110101001100010, vk, vj, vd))
 #define XVFSUB_S(vd, vj, vk)         EMIT(type_3R(0b01110101001100101, vk, vj, vd))
@@ -1833,14 +1901,58 @@ LSX instruction starts with V, LASX instruction starts with XV.
 #define XVFMAXA_D(vd, vj, vk)        EMIT(type_3R(0b01110101010000010, vk, vj, vd))
 #define XVFMINA_S(vd, vj, vk)        EMIT(type_3R(0b01110101010000101, vk, vj, vd))
 #define XVFMINA_D(vd, vj, vk)        EMIT(type_3R(0b01110101010000110, vk, vj, vd))
-#define XVFCVT_H_S(vd, vj, vk)       EMIT(type_3R(0b01110101010001100, vk, vj, vd))
-#define XVFCVT_S_D(vd, vj, vk)       EMIT(type_3R(0b01110101010001101, vk, vj, vd))
-#define XVFTINTRNE_W_D(vd, vj, vk)   EMIT(type_3R(0b01110101010010111, vk, vj, vd))
-#define XVFTINTRZ_W_D(vd, vj, vk)    EMIT(type_3R(0b01110101010010110, vk, vj, vd))
-#define XVFTINTRP_W_D(vd, vj, vk)    EMIT(type_3R(0b01110101010010101, vk, vj, vd))
-#define XVFTINTRM_W_D(vd, vj, vk)    EMIT(type_3R(0b01110101010010100, vk, vj, vd))
-#define XVFTINT_W_D(vd, vj, vk)      EMIT(type_3R(0b01110101010010011, vk, vj, vd))
-#define XVFFINT_S_L(vd, vj, vk)      EMIT(type_3R(0b01110101010010000, vk, vj, vd))
+#define XVFRINT_S(xd, xj)            EMIT(type_2R(0b0111011010011101001101, xj, xd))
+#define XVFRINT_D(xd, xj)            EMIT(type_2R(0b0111011010011101001110, xj, xd))
+#define XVFRINTRM_S(xd, xj)          EMIT(type_2R(0b0111011010011101010001, xj, xd))
+#define XVFRINTRM_D(xd, xj)          EMIT(type_2R(0b0111011010011101010010, xj, xd))
+#define XVFRINTRP_S(xd, xj)          EMIT(type_2R(0b0111011010011101010101, xj, xd))
+#define XVFRINTRP_D(xd, xj)          EMIT(type_2R(0b0111011010011101010110, xj, xd))
+#define XVFRINTRZ_S(xd, xj)          EMIT(type_2R(0b0111011010011101011001, xj, xd))
+#define XVFRINTRZ_D(xd, xj)          EMIT(type_2R(0b0111011010011101011010, xj, xd))
+#define XVFRINTRNE_S(xd, xj)         EMIT(type_2R(0b0111011010011101011101, xj, xd))
+#define XVFRINTRNE_D(xd, xj)         EMIT(type_2R(0b0111011010011101011110, xj, xd))
+#define XVFCVTL_S_H(xd, xj)          EMIT(type_2R(0b0111011010011101111010, xj, xd))
+#define XVFCVTH_S_H(xd, xj)          EMIT(type_2R(0b0111011010011101111011, xj, xd))
+#define XVFCVTL_D_S(xd, xj)          EMIT(type_2R(0b0111011010011101111100, xj, xd))
+#define XVFCVTH_D_S(xd, xj)          EMIT(type_2R(0b0111011010011101111101, xj, xd))
+#define XVFFINT_S_W(xd, xj)          EMIT(type_2R(0b0111011010011110000000, xj, xd))
+#define XVFFINT_S_WU(xd, xj)         EMIT(type_2R(0b0111011010011110000001, xj, xd))
+#define XVFFINT_D_L(xd, xj)          EMIT(type_2R(0b0111011010011110000010, xj, xd))
+#define XVFFINT_D_LU(xd, xj)         EMIT(type_2R(0b0111011010011110000011, xj, xd))
+#define XVFFINTL_D_W(xd, xj)         EMIT(type_2R(0b0111011010011110000100, xj, xd))
+#define XVFFINTH_D_W(xd, xj)         EMIT(type_2R(0b0111011010011110000101, xj, xd))
+#define XVFTINT_W_S(xd, xj)          EMIT(type_2R(0b0111011010011110001100, xj, xd))
+#define XVFTINT_L_D(xd, xj)          EMIT(type_2R(0b0111011010011110001101, xj, xd))
+#define XVFTINTRM_W_S(xd, xj)        EMIT(type_2R(0b0111011010011110001110, xj, xd))
+#define XVFTINTRM_L_D(xd, xj)        EMIT(type_2R(0b0111011010011110001111, xj, xd))
+#define XVFTINTRP_W_S(xd, xj)        EMIT(type_2R(0b0111011010011110010000, xj, xd))
+#define XVFTINTRP_L_D(xd, xj)        EMIT(type_2R(0b0111011010011110010001, xj, xd))
+#define XVFTINTRZ_W_S(xd, xj)        EMIT(type_2R(0b0111011010011110010010, xj, xd))
+#define XVFTINTRZ_L_D(xd, xj)        EMIT(type_2R(0b0111011010011110010011, xj, xd))
+#define XVFTINTRNE_W_S(xd, xj)       EMIT(type_2R(0b0111011010011110010100, xj, xd))
+#define XVFTINTRNE_L_D(xd, xj)       EMIT(type_2R(0b0111011010011110010101, xj, xd))
+#define XVFTINT_WU_S(xd, xj)         EMIT(type_2R(0b0111011010011110010110, xj, xd))
+#define XVFTINT_LU_D(xd, xj)         EMIT(type_2R(0b0111011010011110010111, xj, xd))
+#define XVFTINTRZ_WU_S(xd, xj)       EMIT(type_2R(0b0111011010011110011100, xj, xd))
+#define XVFTINTRZ_LU_D(xd, xj)       EMIT(type_2R(0b0111011010011110011101, xj, xd))
+#define XVFTINTL_L_S(xd, xj)         EMIT(type_2R(0b0111011010011110100000, xj, xd))
+#define XVFTINTH_L_S(xd, xj)         EMIT(type_2R(0b0111011010011110100001, xj, xd))
+#define XVFTINTRML_L_S(xd, xj)       EMIT(type_2R(0b0111011010011110100010, xj, xd))
+#define XVFTINTRMH_L_S(xd, xj)       EMIT(type_2R(0b0111011010011110100011, xj, xd))
+#define XVFTINTRPL_L_S(xd, xj)       EMIT(type_2R(0b0111011010011110100100, xj, xd))
+#define XVFTINTRPH_L_S(xd, xj)       EMIT(type_2R(0b0111011010011110100101, xj, xd))
+#define XVFTINTRZL_L_S(xd, xj)       EMIT(type_2R(0b0111011010011110100110, xj, xd))
+#define XVFTINTRZH_L_S(xd, xj)       EMIT(type_2R(0b0111011010011110100111, xj, xd))
+#define XVFTINTRNEL_L_S(xd, xj)      EMIT(type_2R(0b0111011010011110101000, xj, xd))
+#define XVFTINTRNEH_L_S(xd, xj)      EMIT(type_2R(0b0111011010011110101001, xj, xd))
+#define XVFCVT_H_S(xd, xj, xk)       EMIT(type_3R(0b01110101010001100, xk, xj, xd))
+#define XVFCVT_S_D(xd, xj, xk)       EMIT(type_3R(0b01110101010001101, xk, xj, xd))
+#define XVFFINT_S_L(xd, xj, xk)      EMIT(type_3R(0b01110101010010000, xk, xj, xd))
+#define XVFTINT_W_D(xd, xj, xk)      EMIT(type_3R(0b01110101010010011, xk, xj, xd))
+#define XVFTINTRM_W_D(xd, xj, xk)    EMIT(type_3R(0b01110101010010100, xk, xj, xd))
+#define XVFTINTRP_W_D(xd, xj, xk)    EMIT(type_3R(0b01110101010010101, xk, xj, xd))
+#define XVFTINTRZ_W_D(xd, xj, xk)    EMIT(type_3R(0b01110101010010110, xk, xj, xd))
+#define XVFTINTRNE_W_D(xd, xj, xk)   EMIT(type_3R(0b01110101010010111, xk, xj, xd))
 #define XVSEQ_B(vd, vj, vk)          EMIT(type_3R(0b01110100000000000, vk, vj, vd))
 #define XVSEQ_H(vd, vj, vk)          EMIT(type_3R(0b01110100000000001, vk, vj, vd))
 #define XVSEQ_W(vd, vj, vk)          EMIT(type_3R(0b01110100000000010, vk, vj, vd))
@@ -1890,6 +2002,10 @@ LSX instruction starts with V, LASX instruction starts with XV.
 #define XVSHUF_H(vd, vj, vk)         EMIT(type_3R(0b01110101011110101, vk, vj, vd))
 #define XVSHUF_W(vd, vj, vk)         EMIT(type_3R(0b01110101011110110, vk, vj, vd))
 #define XVSHUF_D(vd, vj, vk)         EMIT(type_3R(0b01110101011110111, vk, vj, vd))
+#define XVSHUF4I_B(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100100, imm8, vj, vd))
+#define XVSHUF4I_H(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100101, imm8, vj, vd))
+#define XVSHUF4I_W(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100110, imm8, vj, vd))
+#define XVSHUF4I_D(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100111, imm8, vj, vd))
 #define XVPERM_W(vd, vj, vk)         EMIT(type_3R(0b01110101011111010, vk, vj, vd))
 #define XVPERMI_W(vd, vj, imm8)      EMIT(type_2RI8(0b01110111111001, imm8, vj, vd))
 #define XVPERMI_D(vd, vj, imm8)      EMIT(type_2RI8(0b01110111111010, imm8, vj, vd))
@@ -1920,7 +2036,7 @@ LSX instruction starts with V, LASX instruction starts with XV.
 #define VPCNT_D(vd, vj)              EMIT(type_2R(0b0111001010011100001011, vj, vd))
 #define VPICKVE2GR_B(rd, vj, imm4)   EMIT(type_2RI4(0b011100101110111110, imm4, vj, rd))
 #define VPICKVE2GR_H(rd, vj, imm3)   EMIT(type_2RI3(0b0111001011101111110, imm3, vj, rd))
-#define VPICKVE2GR_W(rd, vj, imm2)   EMIT(type_2RI1(0b01110010111011111110, imm2, vj, rd))
+#define VPICKVE2GR_W(rd, vj, imm2)   EMIT(type_2RI2(0b01110010111011111110, imm2, vj, rd))
 #define VPICKVE2GR_D(rd, vj, imm1)   EMIT(type_2RI1(0b011100101110111111110, imm1, vj, rd))
 #define VPICKVE2GR_BU(rd, vj, imm4)  EMIT(type_2RI4(0b011100101111001110, imm4, vj, rd))
 #define VPICKVE2GR_HU(rd, vj, imm3)  EMIT(type_2RI3(0b0111001011110011110, imm3, vj, rd))
@@ -1946,6 +2062,153 @@ LSX instruction starts with V, LASX instruction starts with XV.
 #define VNEG_W(vd, vj)              EMIT(type_2R(0b0111011010011100001110, vj, vd))
 #define VNEG_D(vd, vj)              EMIT(type_2R(0b0111011010011100001111, vj, vd))
 
+#define XVLD(vd, rj, imm12)         EMIT(type_2RI12(0b0010110010, imm12, rj, vd))
+#define XVST(vd, rj, imm12)         EMIT(type_2RI12(0b0010110011, imm12, rj, vd))
+#define XVLDX(vd, vj, vk)           EMIT(type_3R(0b00111000010010000, vk, vj, vd))
+#define XVSTX(vd, vj, vk)           EMIT(type_3R(0b00111000010011000, vk, vj, vd))
+
+#define XVHSELI_D(vd, vj, imm5)      EMIT(type_2RI5(0b01110110100111111, imm5, vj, vd))
+#define XVROTRI_B(vd, vj, imm3)      EMIT(type_2RI3(0b0111011010100000001, imm3, vj, vd))
+#define XVROTRI_H(vd, vj, imm4)      EMIT(type_2RI4(0b011101101010000001, imm4, vj, vd))
+#define XVROTRI_W(vd, vj, imm5)      EMIT(type_2RI5(0b01110110101000001, imm5, vj, vd))
+#define XVROTRI_D(vd, vj, imm6)      EMIT(type_2RI6(0b0111011010100001, imm6, vj, vd))
+#define XVSRLRI_B(vd, vj, imm3)      EMIT(type_2RI3(0b0111011010100100001, imm3, vj, vd))
+#define XVSRLRI_H(vd, vj, imm4)      EMIT(type_2RI4(0b011101101010010001, imm4, vj, vd))
+#define XVSRLRI_W(vd, vj, imm5)      EMIT(type_2RI5(0b01110110101001001, imm5, vj, vd))
+#define XVSRLRI_D(vd, vj, imm6)      EMIT(type_2RI6(0b0111011010100101, imm6, vj, vd))
+#define XVSRARI_B(vd, vj, imm3)      EMIT(type_2RI3(0b0111011010101000001, imm3, vj, vd))
+#define XVSRARI_H(vd, vj, imm4)      EMIT(type_2RI4(0b011101101010100001, imm4, vj, vd))
+#define XVSRARI_W(vd, vj, imm5)      EMIT(type_2RI5(0b01110110101010001, imm5, vj, vd))
+#define XVSRARI_D(vd, vj, imm6)      EMIT(type_2RI6(0b0111011010101001, imm6, vj, vd))
+#define XVINSGR2VR_W(vd, vj, imm3)   EMIT(type_2RI3(0b0111011011101011110, imm3, vj, vd))
+#define XVINSGR2VR_D(vd, vj, imm2)   EMIT(type_2RI2(0b01110110111010111110, imm2, vj, vd))
+#define XVPICKVE2GR_W(vd, vj, imm3)  EMIT(type_2RI3(0b0111011011101111110, imm3, vj, vd))
+#define XVPICKVE2GR_D(vd, vj, imm2)  EMIT(type_2RI2(0b01110110111011111110, imm2, vj, vd))
+#define XVPICKVE2GR_WU(vd, vj, imm3) EMIT(type_2RI3(0b0111011011110011110, imm3, vj, vd))
+#define XVPICKVE2GR_DU(vd, vj, imm2) EMIT(type_2RI2(0b01110110111100111110, imm2, vj, vd))
+#define XVREPL128VEI_B(vd, vj, imm4) EMIT(type_2RI4(0b011101101111011110, imm4, vj, vd))
+#define XVREPL128VEI_H(vd, vj, imm3) EMIT(type_2RI3(0b0111011011110111110, imm3, vj, vd))
+#define XVREPL128VEI_W(vd, vj, imm2) EMIT(type_2RI2(0b01110110111101111110, imm2, vj, vd))
+#define XVREPL128VEI_D(vd, vj, imm1) EMIT(type_2RI1(0b011101101111011111110, imm1, vj, vd))
+#define XVINSVE0_W(vd, vj, imm3)     EMIT(type_2RI3(0b0111011011111111110, imm3, vj, vd))
+#define XVINSVE0_D(vd, vj, imm2)     EMIT(type_2RI2(0b01110110111111111110, imm2, vj, vd))
+#define XVPICKVE_W(vd, vj, imm3)     EMIT(type_2RI3(0b0111011100000011110, imm3, vj, vd))
+#define XVPICKVE_D(vd, vj, imm2)     EMIT(type_2RI2(0b01110111000000111110, imm2, vj, vd))
+#define XVREPLVE0_B(xd, xj)          EMIT(type_2R(0b0111011100000111000000, xj, xd))
+#define XVREPLVE0_H(xd, xj)          EMIT(type_2R(0b0111011100000111100000, xj, xd))
+#define XVREPLVE0_W(xd, xj)          EMIT(type_2R(0b0111011100000111110000, xj, xd))
+#define XVREPLVE0_D(xd, xj)          EMIT(type_2R(0b0111011100000111111000, xj, xd))
+#define XVREPLVE0_Q(xd, xj)          EMIT(type_2R(0b0111011100000111111100, xj, xd))
+#define XVEXTL_Q_D(xd, xj)           EMIT(type_2R(0b0111011100001001000000, xj, xd))
+#define XVEXTL_QU_DU(xd, xj)         EMIT(type_2R(0b0111011100001101000000, xj, xd))
+#define XVSLLWIL_H_B(vd, vj, imm3)   EMIT(type_2RI3(0b0111011100001000001, imm3, vj, vd))
+#define XVSLLWIL_W_H(vd, vj, imm4)   EMIT(type_2RI4(0b011101110000100001, imm4, vj, vd))
+#define XVSLLWIL_D_W(vd, vj, imm5)   EMIT(type_2RI5(0b01110111000010001, imm5, vj, vd))
+#define XVSLLWIL_HU_BU(vd, vj, imm3) EMIT(type_2RI3(0b0111011100001100001, imm3, vj, vd))
+#define XVSLLWIL_WU_HU(vd, vj, imm4) EMIT(type_2RI4(0b011101110000110001, imm4, vj, vd))
+#define XVSLLWIL_DU_WU(vd, vj, imm5) EMIT(type_2RI5(0b01110111000011001, imm5, vj, vd))
+#define XVBITCLRI_B(vd, vj, imm3)    EMIT(type_2RI3(0b0111011100010000001, imm3, vj, vd))
+#define XVBITCLRI_H(vd, vj, imm4)    EMIT(type_2RI4(0b011101110001000001, imm4, vj, vd))
+#define XVBITCLRI_W(vd, vj, imm5)    EMIT(type_2RI5(0b01110111000100001, imm5, vj, vd))
+#define XVBITCLRI_D(vd, vj, imm6)    EMIT(type_2RI6(0b0111011100010001, imm6, vj, vd))
+#define XVBITSETI_B(vd, vj, imm3)    EMIT(type_2RI3(0b0111011100010100001, imm3, vj, vd))
+#define XVBITSETI_H(vd, vj, imm4)    EMIT(type_2RI4(0b011101110001010001, imm4, vj, vd))
+#define XVBITSETI_W(vd, vj, imm5)    EMIT(type_2RI5(0b01110111000101001, imm5, vj, vd))
+#define XVBITSETI_D(vd, vj, imm6)    EMIT(type_2RI6(0b0111011100010101, imm6, vj, vd))
+#define XVBITREVI_B(vd, vj, imm3)    EMIT(type_2RI3(0b0111011100011000001, imm3, vj, vd))
+#define XVBITREVI_H(vd, vj, imm4)    EMIT(type_2RI4(0b011101110001100001, imm4, vj, vd))
+#define XVBITREVI_W(vd, vj, imm5)    EMIT(type_2RI5(0b01110111000110001, imm5, vj, vd))
+#define XVBITREVI_D(vd, vj, imm6)    EMIT(type_2RI6(0b0111011100011001, imm6, vj, vd))
+#define XVSAT_B(vd, vj, imm3)        EMIT(type_2RI3(0b0111011100100100001, imm3, vj, vd))
+#define XVSAT_H(vd, vj, imm4)        EMIT(type_2RI4(0b011101110010010001, imm4, vj, vd))
+#define XVSAT_W(vd, vj, imm5)        EMIT(type_2RI5(0b01110111001001001, imm5, vj, vd))
+#define XVSAT_D(vd, vj, imm6)        EMIT(type_2RI6(0b0111011100100101, imm6, vj, vd))
+#define XVSAT_BU(vd, vj, imm3)       EMIT(type_2RI3(0b0111011100101000001, imm3, vj, vd))
+#define XVSAT_HU(vd, vj, imm4)       EMIT(type_2RI4(0b011101110010100001, imm4, vj, vd))
+#define XVSAT_WU(vd, vj, imm5)       EMIT(type_2RI5(0b01110111001010001, imm5, vj, vd))
+#define XVSAT_DU(vd, vj, imm6)       EMIT(type_2RI6(0b0111011100101001, imm6, vj, vd))
+#define XVSLLI_B(vd, vj, imm3)       EMIT(type_2RI3(0b0111011100101100001, imm3, vj, vd))
+#define XVSLLI_H(vd, vj, imm4)       EMIT(type_2RI4(0b011101110010110001, imm4, vj, vd))
+#define XVSLLI_W(vd, vj, imm5)       EMIT(type_2RI5(0b01110111001011001, imm5, vj, vd))
+#define XVSLLI_D(vd, vj, imm6)       EMIT(type_2RI6(0b0111011100101101, imm6, vj, vd))
+#define XVSRLI_B(vd, vj, imm3)       EMIT(type_2RI3(0b0111011100110000001, imm3, vj, vd))
+#define XVSRLI_H(vd, vj, imm4)       EMIT(type_2RI4(0b011101110011000001, imm4, vj, vd))
+#define XVSRLI_W(vd, vj, imm5)       EMIT(type_2RI5(0b01110111001100001, imm5, vj, vd))
+#define XVSRLI_D(vd, vj, imm6)       EMIT(type_2RI6(0b0111011100110001, imm6, vj, vd))
+#define XVSRAI_B(vd, vj, imm3)       EMIT(type_2RI3(0b0111011100110100001, imm3, vj, vd))
+#define XVSRAI_H(vd, vj, imm4)       EMIT(type_2RI4(0b011101110011010001, imm4, vj, vd))
+#define XVSRAI_W(vd, vj, imm5)       EMIT(type_2RI5(0b01110111001101001, imm5, vj, vd))
+#define XVSRAI_D(vd, vj, imm6)       EMIT(type_2RI6(0b0111011100110101, imm6, vj, vd))
+#define XVSRLNI_B_H(vd, vj, imm4)    EMIT(type_2RI4(0b011101110100000001, imm4, vj, vd))
+#define XVSRLNI_H_W(vd, vj, imm5)    EMIT(type_2RI5(0b01110111010000001, imm5, vj, vd))
+#define XVSRLNI_W_D(vd, vj, imm6)    EMIT(type_2RI6(0b0111011101000001, imm6, vj, vd))
+#define XVSRLNI_D_Q(vd, vj, imm7)    EMIT(type_2RI7(0b011101110100001, imm7, vj, vd))
+#define XVSRLRNI_B_H(vd, vj, imm4)   EMIT(type_2RI4(0b011101110100010001, imm4, vj, vd))
+#define XVSRLRNI_H_W(vd, vj, imm5)   EMIT(type_2RI5(0b01110111010001001, imm5, vj, vd))
+#define XVSRLRNI_W_D(vd, vj, imm6)   EMIT(type_2RI6(0b0111011101000101, imm6, vj, vd))
+#define XVSRLRNI_D_Q(vd, vj, imm7)   EMIT(type_2RI7(0b011101110100011, imm7, vj, vd))
+#define XVSSRLNI_B_H(vd, vj, imm4)   EMIT(type_2RI4(0b011101110100100001, imm4, vj, vd))
+#define XVSSRLNI_H_W(vd, vj, imm5)   EMIT(type_2RI5(0b01110111010010001, imm5, vj, vd))
+#define XVSSRLNI_W_D(vd, vj, imm6)   EMIT(type_2RI6(0b0111011101001001, imm6, vj, vd))
+#define XVSSRLNI_D_Q(vd, vj, imm7)   EMIT(type_2RI7(0b011101110100101, imm7, vj, vd))
+#define XVSSRLNI_BU_H(vd, vj, imm4)  EMIT(type_2RI4(0b011101110100110001, imm4, vj, vd))
+#define XVSSRLNI_HU_W(vd, vj, imm5)  EMIT(type_2RI5(0b01110111010011001, imm5, vj, vd))
+#define XVSSRLNI_WU_D(vd, vj, imm6)  EMIT(type_2RI6(0b0111011101001101, imm6, vj, vd))
+#define XVSSRLNI_DU_Q(vd, vj, imm7)  EMIT(type_2RI7(0b011101110100111, imm7, vj, vd))
+#define XVSSRLRNI_B_H(vd, vj, imm4)  EMIT(type_2RI4(0b011101110101000001, imm4, vj, vd))
+#define XVSSRLRNI_H_W(vd, vj, imm5)  EMIT(type_2RI5(0b01110111010100001, imm5, vj, vd))
+#define XVSSRLRNI_W_D(vd, vj, imm6)  EMIT(type_2RI6(0b0111011101010001, imm6, vj, vd))
+#define XVSSRLRNI_D_Q(vd, vj, imm7)  EMIT(type_2RI7(0b011101110101001, imm7, vj, vd))
+#define XVSSRLRNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011101110101010001, imm4, vj, vd))
+#define XVSSRLRNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110111010101001, imm5, vj, vd))
+#define XVSSRLRNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111011101010101, imm6, vj, vd))
+#define XVSSRLRNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011101110101011, imm7, vj, vd))
+#define XVSRANI_B_H(vd, vj, imm4)    EMIT(type_2RI4(0b011101110101100001, imm4, vj, vd))
+#define XVSRANI_H_W(vd, vj, imm5)    EMIT(type_2RI5(0b01110111010110001, imm5, vj, vd))
+#define XVSRANI_W_D(vd, vj, imm6)    EMIT(type_2RI6(0b0111011101011001, imm6, vj, vd))
+#define XVSRANI_D_Q(vd, vj, imm7)    EMIT(type_2RI7(0b011101110101101, imm7, vj, vd))
+#define XVSRARNI_B_H(vd, vj, imm4)   EMIT(type_2RI4(0b011101110101110001, imm4, vj, vd))
+#define XVSRARNI_H_W(vd, vj, imm5)   EMIT(type_2RI5(0b01110111010111001, imm5, vj, vd))
+#define XVSRARNI_W_D(vd, vj, imm6)   EMIT(type_2RI6(0b0111011101011101, imm6, vj, vd))
+#define XVSRARNI_D_Q(vd, vj, imm7)   EMIT(type_2RI7(0b011101110101111, imm7, vj, vd))
+#define XVSSRANI_B_H(vd, vj, imm4)   EMIT(type_2RI4(0b011101110110000001, imm4, vj, vd))
+#define XVSSRANI_H_W(vd, vj, imm5)   EMIT(type_2RI5(0b01110111011000001, imm5, vj, vd))
+#define XVSSRANI_W_D(vd, vj, imm6)   EMIT(type_2RI6(0b0111011101100001, imm6, vj, vd))
+#define XVSSRANI_D_Q(vd, vj, imm7)   EMIT(type_2RI7(0b011101110110001, imm7, vj, vd))
+#define XVSSRANI_BU_H(vd, vj, imm4)  EMIT(type_2RI4(0b011101110110010001, imm4, vj, vd))
+#define XVSSRANI_HU_W(vd, vj, imm5)  EMIT(type_2RI5(0b01110111011001001, imm5, vj, vd))
+#define XVSSRANI_WU_D(vd, vj, imm6)  EMIT(type_2RI6(0b0111011101100101, imm6, vj, vd))
+#define XVSSRANI_DU_Q(vd, vj, imm7)  EMIT(type_2RI7(0b011101110110011, imm7, vj, vd))
+#define XVSSRARNI_B_H(vd, vj, imm4)  EMIT(type_2RI4(0b011101110110100001, imm4, vj, vd))
+#define XVSSRARNI_H_W(vd, vj, imm5)  EMIT(type_2RI5(0b01110111011010001, imm5, vj, vd))
+#define XVSSRARNI_W_D(vd, vj, imm6)  EMIT(type_2RI6(0b0111011101101001, imm6, vj, vd))
+#define XVSSRARNI_D_Q(vd, vj, imm7)  EMIT(type_2RI7(0b011101110110101, imm7, vj, vd))
+#define XVSSRARNI_BU_H(vd, vj, imm4) EMIT(type_2RI4(0b011101110110110001, imm4, vj, vd))
+#define XVSSRARNI_HU_W(vd, vj, imm5) EMIT(type_2RI5(0b01110111011011001, imm5, vj, vd))
+#define XVSSRARNI_WU_D(vd, vj, imm6) EMIT(type_2RI6(0b0111011101101101, imm6, vj, vd))
+#define XVSSRARNI_DU_Q(vd, vj, imm7) EMIT(type_2RI7(0b011101110110111, imm7, vj, vd))
+#define XVEXTRINS_D(vd, vj, imm8)    EMIT(type_2RI8(0b01110111100000, imm8, vj, vd))
+#define XVEXTRINS_W(vd, vj, imm8)    EMIT(type_2RI8(0b01110111100001, imm8, vj, vd))
+#define XVEXTRINS_H(vd, vj, imm8)    EMIT(type_2RI8(0b01110111100010, imm8, vj, vd))
+#define XVEXTRINS_B(vd, vj, imm8)    EMIT(type_2RI8(0b01110111100011, imm8, vj, vd))
+#define XVSHUF4I_B(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100100, imm8, vj, vd))
+#define XVSHUF4I_H(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100101, imm8, vj, vd))
+#define XVSHUF4I_W(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100110, imm8, vj, vd))
+#define XVSHUF4I_D(vd, vj, imm8)     EMIT(type_2RI8(0b01110111100111, imm8, vj, vd))
+#define XVBITSELI_B(vd, vj, imm8)    EMIT(type_2RI8(0b01110111110001, imm8, vj, vd))
+#define XVANDI_B(vd, vj, imm8)       EMIT(type_2RI8(0b01110111110100, imm8, vj, vd))
+#define XVORI_B(vd, vj, imm8)        EMIT(type_2RI8(0b01110111110101, imm8, vj, vd))
+#define XVXORI_B(vd, vj, imm8)       EMIT(type_2RI8(0b01110111110110, imm8, vj, vd))
+#define XVNORI_B(vd, vj, imm8)       EMIT(type_2RI8(0b01110111110111, imm8, vj, vd))
+
+#define XVFMADD_S(xd, xj, xk, xa)  EMIT(type_4R(0b000010100001, xa, xk, xj, xd))
+#define XVFMSUB_S(xd, xj, xk, xa)  EMIT(type_4R(0b000010100101, xa, xk, xj, xd))
+#define XVFNMADD_S(xd, xj, xk, xa) EMIT(type_4R(0b000010101001, xa, xk, xj, xd))
+#define XVFNMSUB_S(xd, xj, xk, xa) EMIT(type_4R(0b000010101101, xa, xk, xj, xd))
+#define XVFMADD_D(xd, xj, xk, xa)  EMIT(type_4R(0b000010100010, xa, xk, xj, xd))
+#define XVFMSUB_D(xd, xj, xk, xa)  EMIT(type_4R(0b000010100110, xa, xk, xj, xd))
+#define XVFNMADD_D(xd, xj, xk, xa) EMIT(type_4R(0b000010101010, xa, xk, xj, xd))
+#define XVFNMSUB_D(xd, xj, xk, xa) EMIT(type_4R(0b000010101110, xa, xk, xj, xd))
 ////////////////////////////////////////////////////////////////////////////////
 // (undocumented) LBT extension instructions
 
diff --git a/src/dynarec/la64/la64_printer.c b/src/dynarec/la64/la64_printer.c
index b044436b..0c80f84a 100644
--- a/src/dynarec/la64/la64_printer.c
+++ b/src/dynarec/la64/la64_printer.c
@@ -71,7 +71,6 @@ const char* la64_print(uint32_t opcode, uintptr_t addr)
 #define Rc     a.c
 #define imm    a.i
 #define imm_up a.u
-
     if (isMask(opcode, "00000000000100000kkkkkjjjjjddddd", &a)) {
         snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "ADD.W", Xt[Rd], Xt[Rj], Xt[Rk]);
         return buff;
@@ -756,6 +755,14 @@ const char* la64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "%-15s %s, %s", "MOVCF2GR", Xt[Rd], FCCt[Rc]);
         return buff;
     }
+    if (isMask(opcode, "0000000100011001001001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "FCVT.D.S", Ft[Rd], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0000000100011001000110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "FCVT.S.D", Ft[Rd], Ft[Rj]);
+        return buff;
+    }
     if (isMask(opcode, "0000000100011010000001jjjjjddddd", &a)) {
         snprintf(buff, sizeof(buff), "%-15s %s, %s", "FTINTRM.W.S", Ft[Rd], Ft[Rj]);
         return buff;
@@ -2289,6 +2296,426 @@ const char* la64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VEXTRINS.B", Vt[Rd], Vt[Rj], imm);
         return buff;
     }
+    if (isMask(opcode, "011100101110101110iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VINSGR2VR.B", Vt[Rd], Xt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001011101011110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VINSGR2VR.H", Vt[Rd], Xt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110010111010111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VINSGR2VR.W", Vt[Rd], Xt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100101110101111110ijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VINSGR2VR.D", Vt[Rd], Xt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100101110111110iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.B", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001011101111110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.H", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110010111011111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.W", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100101110111111110ijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.D", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100101111001110iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.BU", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001011110011110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.HU", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110010111100111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.WU", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100101111001111110ijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPICKVE2GR.DU", Xt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100101111011110iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VREPLVEI.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001011110111110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VREPLVEI.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110010111101111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VREPLVEI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100101111011111110ijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VREPLVEI.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100001000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLWIL.H.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110000100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLWIL.W.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011000010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLWIL.D.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100001001000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXTL.Q.D", Vt[Rd], Vt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100001100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLWIL.HU.BU", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110000110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLWIL.WU.HU", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011000011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLWIL.DU.WU", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100001101000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXTL.QU.DU", Vt[Rd], Vt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100010000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITCLRI.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110001000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITCLRI.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011000100001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITCLRI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100010001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITCLRI.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100010100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITSETI.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110001010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITSETI.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011000101001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITSETI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100010101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITSETI.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100011000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITREVI.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110001100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITREVI.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011000110001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITREVI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100011001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VBITREVI.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100100100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110010010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011001001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100100101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100101000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.BU", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110010100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.HU", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011001010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.WU", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100101001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSAT.DU", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100101100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLI.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110010110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLI.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011001011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100101101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSLLI.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100110000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLI.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110011000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLI.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011001100001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100110001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLI.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100110100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRAI.B", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110011010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRAI.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011001101001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRAI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001100110101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRAI.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLNI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010000001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLNI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101000001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLNI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100001iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLNI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101001001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100101iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLRNI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLRNI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101000101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLRNI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100011iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRLRNI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.BU.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.HU.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101001101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.WU.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110100111iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLNI.DU.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010100001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101010001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101001iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.BU.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010101001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.HU.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101010101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.WU.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101011iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRLRNI.DU.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRANI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010110001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRANI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101011001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRANI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101101iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRANI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRARNI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011010111001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRARNI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101011101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRARNI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110101111iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSRARNI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011011000001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101100001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110001iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.BU.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011011001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.HU.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101100101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.WU.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110011iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRANI.DU.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.B.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011011010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.H.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101101001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.W.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110101iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.D.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.BU.H", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011011011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.HU.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111001101101101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.WU.D", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011100110110111iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VSSRARNI.DU.Q", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110011111001iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "VPERMI.W", Vt[Rd], Vt[Rj], imm);
+        return buff;
+    }
     if (isMask(opcode, "0010110000iiiiiiiiiiiijjjjjddddd", &a)) {
         snprintf(buff, sizeof(buff), "%-15s %s, %s, %ld", "VLD", Vt[Rd], Xt[Rj], signExtend(imm, 12));
         return buff;
@@ -3081,6 +3508,14 @@ const char* la64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SUNE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
         return buff;
     }
+    if (isMask(opcode, "0010110010iiiiiiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %ld", "XVLD", XVt[Rd], Xt[Rj], signExtend(imm, 12));
+        return buff;
+    }
+    if (isMask(opcode, "0010110011iiiiiiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %ld", "XVST", XVt[Rd], Xt[Rj], signExtend(imm, 12));
+        return buff;
+    }
     if (isMask(opcode, "00000000000000001000000000101000", &a)) {
         snprintf(buff, sizeof(buff), "X64CLRSM");
         return buff;
@@ -3533,7 +3968,3286 @@ const char* la64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "%-15s %s, %lu", "X64RCLI.D", Xt[Rj], imm);
         return buff;
     }
-
+    if (isMask(opcode, "0000000100010100111000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "FCVT.LD.D", Ft[Rd], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0000000100010100111001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "FCVT.UD.D", Ft[Rd], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00000001000101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s,", "FCVT.D.LD", Ft[Rd], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "0000000100010100110000jjjjj000cc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "MOVGR2FCSR", FCSRt[Rc], Xt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0000000100010100110010000ccddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "MOVFCSR2GR", Xt[Rd], FCSRt[Rc]);
+        return buff;
+    }
+    if (isMask(opcode, "0000000100010100110100jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "MOVFR2CF", FCCt[Rc], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "000000010001010011010100cccddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "MOVCF2FR", Ft[Rd], FCCt[Rc]);
+        return buff;
+    }
+    if (isMask(opcode, "0000000100010100110110jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "MOVGR2CF", FCCt[Rc], Xt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "000000010001010011011100cccddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "MOVCF2GR", Xt[Rd], FCCt[Rc]);
+        return buff;
+    }
+    if (isMask(opcode, "010010iiiiiiiiiiiiiiii00cccuuuuu", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %ld", "BCEQZ", FCCt[Rc], signExtend((imm + (imm_up << 16)) << 2, 23));
+        return buff;
+    }
+    if (isMask(opcode, "010010iiiiiiiiiiiiiiii01cccuuuuu", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %ld", "BCNEZ", FCCt[Rc], signExtend((imm + (imm_up << 16)) << 2, 23));
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CAF.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SAF.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100010kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CLT.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100011kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SLT.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100011kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SGT.S", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100100kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CEQ.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100101kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SEQ.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100110kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CLE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100111kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SLE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000100111kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SGE.S", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUN.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SUN.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101010kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CULT.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101010kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUGT.S", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101011kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SULT.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101100kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUEQ.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101101kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SUEQ.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101110kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CULE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101110kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUGE.S", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000101111kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SULE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000110000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CNE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000110001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SNE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000110100kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.COR.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000110101kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SOR.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000111000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUNE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100000111001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SUNE.S", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CAF.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SAF.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000010kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CLT.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000011kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SLT.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000011kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SGT.D", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000100kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CEQ.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000101kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SEQ.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000110kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CLE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000111kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SLE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001000111kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SGE.D", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUN.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SUN.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001010kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CULT.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001010kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUGT.D", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001011kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SULT.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001100kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUEQ.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001101kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SUEQ.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001110kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CULE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001110kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUGE.D", FCCt[Rc], Ft[Rk], Ft[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001001111kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SULE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001010000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CNE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001010001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SNE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001010100kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.COR.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001010101kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SOR.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001011000kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.CUNE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100001011001kkkkkjjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "FCMP.SUNE.D", FCCt[Rc], Ft[Rj], Ft[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CAF.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SAF.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CLT.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SLT.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CEQ.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SEQ.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CLE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010100111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SLE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CUN.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SUN.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CULT.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SULT.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CUEQ.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SUEQ.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CULE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010101111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SULE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010110000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CNE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010110001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SNE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010110100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.COR.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SOR.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010111000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CUNE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100010111001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SUNE.S", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CAF.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SAF.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CLT.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SLT.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CEQ.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SEQ.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CLE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100100111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SLE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CUN.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SUN.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CULT.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SULT.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CUEQ.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SUEQ.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CULE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100101111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SULE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100110000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CNE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100110001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SNE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100110100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.COR.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SOR.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100111000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CUNE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100100111001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SUNE.S", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CAF.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SAF.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CLT.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SLT.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CEQ.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SEQ.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CLE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SLE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CUN.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SUN.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CULT.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SULT.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CUEQ.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SUEQ.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CULE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SULE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CNE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SNE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.COR.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SOR.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011011000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.CUNE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100011011001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "VFCMP.SUNE.D", Vt[Rd], Vt[Rj], Vt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CAF.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SAF.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CLT.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SLT.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CEQ.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SEQ.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CLE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SLE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CUN.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SUN.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CULT.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SULT.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CUEQ.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SUEQ.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CULE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SULE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CNE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SNE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.COR.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SOR.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101011000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.CUNE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "00001100101011001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCMP.SUNE.D", Xt[Rd], Xt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSEQ.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSEQ.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSEQ.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSEQ.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLE.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLT.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADD.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADD.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADD.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000011000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUB.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000011001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUB.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000011010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUB.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000011011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUB.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSADD.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010011000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010011001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010011010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010011011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSUB.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010101111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.HU.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.WU.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.DU.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHADDW.QU.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.HU.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.WU.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.DU.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010110111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVHSUBW.QU.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000111100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000111101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000111110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100000111111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001011100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001011101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001011110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001011111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001111100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.H.BU.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001111101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.W.HU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001111110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.D.WU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001111111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWEV.Q.DU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.H.BU.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.W.HU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.D.WU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDWOD.Q.DU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.H.BU.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.W.HU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.D.WU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.Q.DU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWEV.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101011111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101101111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.H.BU.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.W.HU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.D.WU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101111111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADDWOD.Q.DU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.H.BU.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.W.HU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.D.WU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWEV.Q.DU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100100111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100110111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.H.BU.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.W.HU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.D.WU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMULWOD.Q.DU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001100011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWEV.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001001000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.H.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.W.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.D.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.Q.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001101000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.H.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001101001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.W.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.D.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100001101011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUBWOD.Q.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010111000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDA.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010111001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDA.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010111010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDA.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100010111011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADDA.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVABSD.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVG.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAVGR.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011100111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMAX.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100011101111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMIN.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUL.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUL.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUL.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUL.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100010010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100100010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMUH.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADD.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADD.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADD.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMADD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMSUB.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMSUB.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMSUB.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100101010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMSUB.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVDIV.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.BU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.HU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.WU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVMOD.DU", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLL.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLL.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLL.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSLL.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRL.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRL.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRL.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRL.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRA.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRA.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRA.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRA.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVROTR.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVROTR.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVROTR.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111011111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVROTR.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLR.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLR.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLR.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLR.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRAR.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRAR.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRAR.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111100111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRAR.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111101001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111101010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111101011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111101101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRAN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111101110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRAN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111101111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRAN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111110001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLRN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111110010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLRN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111110011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRLRN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRARN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111110110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRARN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111110111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSRARN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111111001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111111010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111111011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111111101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRAN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111111110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRAN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110100111111111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRAN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLRN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLRN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLRN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRARN.B.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRARN.H.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRARN.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000001001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLN.BU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000001010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLN.HU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000001011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLN.WU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRAN.BU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRAN.HU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRAN.WU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLRN.BU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000010010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLRN.HU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRLRN.WU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRARN.BU.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRARN.HU.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSSRARN.WU.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITCLR.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITCLR.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITCLR.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITCLR.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITSET.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITSET.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITSET.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000011111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITSET.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000100000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITREV.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITREV.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITREV.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000100011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVBITREV.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000101100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKEV.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000101101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKEV.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000101110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKEV.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000101111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKEV.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKOD.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKOD.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKOD.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPACKOD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVL.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVL.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVL.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000110111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVL.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVH.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVH.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVH.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVILVH.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKEV.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKEV.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKEV.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101000111111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKEV.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKOD.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKOD.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKOD.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPICKOD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVREPLVE.B", XVt[Rd], XVt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVREPLVE.H", XVt[Rd], XVt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVREPLVE.W", XVt[Rd], XVt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001000111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVREPLVE.D", XVt[Rd], XVt[Rj], Xt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVAND.V", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVOR.V", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001001110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVXOR.V", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001001111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVNOR.V", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVANDN.V", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001010001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVORN.V", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFRSTP.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFRSTP.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001011010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVADD.Q", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001011011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSUB.Q", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001011100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSIGNCOV.B", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001011101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSIGNCOV.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001011110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSIGNCOV.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001011111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSIGNCOV.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001100001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFADD.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001100010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFADD.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001100101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFSUB.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001100110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFSUB.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001110001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMUL.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001110010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMUL.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFDIV.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001110110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFDIV.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001111001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMAX.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001111010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMAX.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001111101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMIN.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101001111110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMIN.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010000001kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMAXA.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010000010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMAXA.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010000101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMINA.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010000110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFMINA.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010001100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCVT.H.S", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010001101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFCVT.S.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010010000kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFFINT.S.L", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010010011kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFTINT.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010010100kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFTINTRM.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010010101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFTINTRP.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010010110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFTINTRZ.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101010010111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVFTINTRNE.W.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101011110101kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSHUF.H", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101011110110kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSHUF.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101011110111kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVSHUF.D", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110101011111010kkkkkjjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "XVPERM.W", XVt[Rd], XVt[Rj], XVt[Rk]);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000000iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSEQI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSEQI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000010iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSEQI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000011iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSEQI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000100iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000101iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000110iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100000111iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001000iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001010iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001011iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLEI.DU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001100iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001101iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001110iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100001111iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010000iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010010iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010011iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLTI.DU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010100iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVADDI.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010101iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVADDI.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010110iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVADDI.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100010111iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVADDI.DU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100011000iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSUBI.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSUBI.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100011010iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSUBI.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100011011iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSUBI.DU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100011100iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBSLL.V", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100011101iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBSRL.V", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100000iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100010iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100011iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100100iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100101iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100110iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100100111iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101000iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101010iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101011iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMAXI.DU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101100iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101101iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101110iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100101111iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVMINI.DU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100110100iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVFRSTPI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100110101iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVFRSTPI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLO.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLO.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLO.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLO.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLZ.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLZ.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLZ.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100000111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVCLZ.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVPCNT.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVPCNT.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVPCNT.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVPCNT.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVNEG.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVNEG.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVNEG.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100001111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVNEG.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100010000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVMSKLTZ.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100010001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVMSKLTZ.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100010010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVMSKLTZ.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100010011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVMSKLTZ.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100010100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVMSKGEZ.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100011000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVMSKNZ.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100100110jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETEQZ.V", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100100111jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETNEZ.V", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101000jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETANYEQZ.B", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101001jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETANYEQZ.H", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101010jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETANYEQZ.W", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101011jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETANYEQZ.D", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101100jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETALLNEZ.B", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101101jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETALLNEZ.H", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101110jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETALLNEZ.W", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100101111jjjjj00ccc", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVSETALLNEZ.D", FCCt[Rc], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100110001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFLOGB.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100110010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFLOGB.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100110101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFCLASS.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100110110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFCLASS.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100111001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFSQRT.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100111010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFSQRT.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100111101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRECIP.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011100111110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRECIP.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101000001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRSQRT.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101000010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRSQRT.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101000101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRECIPE.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101000110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRECIPE.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101001001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRSQRTE.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101001010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRSQRTE.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101001101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINT.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101001110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINT.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101010001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRM.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101010010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRM.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101010101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRP.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101010110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRP.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101011001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRZ.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101011010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRZ.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101011101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRNE.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101011110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFRINTRNE.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101111010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFCVTL.S.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101111011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFCVTH.S.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101111100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFCVTL.D.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011101111101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFCVTH.D.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFFINT.S.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110000001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFFINT.S.WU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110000010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFFINT.D.L", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110000011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFFINT.D.LU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110000100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFFINTL.D.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110000101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFFINTH.D.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110001100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINT.W.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110001101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINT.L.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110001110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRM.W.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110001111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRM.L.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRP.W.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRP.L.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRZ.W.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRZ.L.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRNE.W.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRNE.L.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINT.WU.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110010111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINT.LU.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110011100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRZ.WU.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110011101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRZ.LU.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTL.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTH.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRML.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRMH.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRPL.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRPH.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRZL.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110100111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRZH.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110101000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRNEL.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110101001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVFTINTRNEH.L.S", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.H.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.W.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.D.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.Q.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.HU.BU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.WU.HU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.DU.WU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011110111111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTH.QU.DU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLGR2VR.B", XVt[Rd], Xt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLGR2VR.H", XVt[Rd], Xt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLGR2VR.W", XVt[Rd], Xt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLGR2VR.D", XVt[Rd], Xt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.H.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.W.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.D.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111000111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.W.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.D.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001001jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.D.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001010jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.HU.BU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001011jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.WU.BU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.DU.BU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001101jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.WU.HU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001110jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.DU.HU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010011111001111jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "VEXT2XV.DU.WU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "01110110100111111iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVHSELI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010100000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVROTRI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101101010000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVROTRI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110101000001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVROTRI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010100001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVROTRI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010100100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101101010010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110101001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010100101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010101000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101101010100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110101010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011010101001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011011101011110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVINSGR2VR.W", XVt[Rd], Xt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110111010111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVINSGR2VR.D", XVt[Rd], Xt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011011101111110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPICKVE2GR.W", Xt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110111011111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPICKVE2GR.D", Xt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011011110011110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPICKVE2GR.WU", Xt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110111100111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPICKVE2GR.DU", Xt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101101111011110iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVREPL128VEI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011011110111110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVREPL128VEI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110111101111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVREPL128VEI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101101111011111110ijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVREPL128VEI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011011111111110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVINSVE0.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110110111111111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVINSVE0.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100000011110iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPICKVE.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111000000111110iijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPICKVE.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100000111000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLVE0.B", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100000111100000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLVE0.H", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100000111110000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLVE0.W", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100000111111000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLVE0.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100000111111100jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVREPLVE0.Q", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100001000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLWIL.H.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110000100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLWIL.W.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111000010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLWIL.D.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100001001000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTL.Q.D", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100001100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLWIL.HU.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110000110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLWIL.WU.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111000011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLWIL.DU.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100001101000000jjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s", "XVEXTL.QU.DU", XVt[Rd], XVt[Rj]);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100010000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITCLRI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110001000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITCLRI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111000100001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITCLRI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100010001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITCLRI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100010100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITSETI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110001010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITSETI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111000101001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITSETI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100010101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITSETI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100011000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITREVI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110001100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITREVI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111000110001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITREVI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100011001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITREVI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100100100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110010010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111001001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100100101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100101000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.BU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110010100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.HU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111001010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.WU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100101001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSAT.DU", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100101100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110010110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111001011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100101101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSLLI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100110000001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110011000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111001100001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100110001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100110100001iiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRAI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110011010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRAI.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111001101001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRAI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011100110101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRAI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLNI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010000001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLNI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101000001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLNI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100001iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLNI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRNI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRNI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101000101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRNI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100011iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRLRNI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101001001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100101iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.BU.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.HU.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101001101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.WU.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110100111iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLNI.DU.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010100001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101010001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101001iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.BU.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010101001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.HU.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101010101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.WU.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101011iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRLRNI.DU.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRANI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010110001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRANI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101011001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRANI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101101iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRANI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARNI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111010111001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARNI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101011101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARNI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110101111iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSRARNI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110000001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111011000001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101100001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110001iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110010001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.BU.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111011001001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.HU.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101100101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.WU.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110011iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRANI.DU.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110100001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.B.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111011010001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.H.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101101001iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.W.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110101iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.D.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110110001iiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.BU.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111011011001iiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.HU.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "0111011101101101iiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.WU.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "011101110110111iiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSSRARNI.DU.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100000iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVEXTRINS.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100001iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVEXTRINS.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100010iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVEXTRINS.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100011iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVEXTRINS.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100100iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSHUF4I.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100101iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSHUF4I.H", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100110iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSHUF4I.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111100111iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVSHUF4I.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111110001iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVBITSELI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111110100iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVANDI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111110101iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVORI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111110110iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVXORI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111110111iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVNORI.B", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111111000iiiiiiiiiiiiiddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, 0x%lx", "XVLDI", XVt[Rd], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111111001iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPERMI.W", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111111010iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPERMI.D", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
+    if (isMask(opcode, "01110111111011iiiiiiiijjjjjddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%lx", "XVPERMI.Q", XVt[Rd], XVt[Rj], imm);
+        return buff;
+    }
     snprintf(buff, sizeof(buff), "%08X ???", __builtin_bswap32(opcode));
     return buff;
 }