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| author | Yang Liu <liuyang22@iscas.ac.cn> | 2025-09-22 16:53:52 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-22 10:53:52 +0200 |
| commit | bad4d13c09703c2d8101a8636210ffccb8126fbe (patch) | |
| tree | de33effd06749ae58519b26530f45217d6e3dbc7 /src | |
| parent | 5bfb27d3fa867c5d204d5f7e23507e36b87c82f7 (diff) | |
| download | box64-bad4d13c09703c2d8101a8636210ffccb8126fbe.tar.gz box64-bad4d13c09703c2d8101a8636210ffccb8126fbe.zip | |
[RV64_DYNAREC] Added more avx scalar opcodes (#3028)
Diffstat (limited to 'src')
| -rw-r--r-- | src/dynarec/rv64/dynarec_rv64_avx_66_0f3a.c | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/src/dynarec/rv64/dynarec_rv64_avx_66_0f3a.c b/src/dynarec/rv64/dynarec_rv64_avx_66_0f3a.c index 207a9723..5da46c78 100644 --- a/src/dynarec/rv64/dynarec_rv64_avx_66_0f3a.c +++ b/src/dynarec/rv64/dynarec_rv64_avx_66_0f3a.c @@ -225,6 +225,99 @@ uintptr_t dynarec64_AVX_66_0F3A(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i } else YMM0(gd); break; + case 0x16: + if (rex.w) { + INST_NAME("VPEXTRQ Ed, Gx, Ib"); + } else { + INST_NAME("VPEXTRD Ed, Gx, Ib"); + } + nextop = F8; + GETGX(); + GETED(1); + u8 = F8; + if (rex.w) { + LD(ed, gback, gdoffset + 8 * (u8 & 0x1)); + if (!MODREG) { + SD(ed, wback, fixedaddress); + SMWRITE2(); + } + } else { + if (MODREG) { + LWU(ed, gback, gdoffset + 4 * (u8 & 0x3)); + } else { + LW(ed, gback, gdoffset + 4 * (u8 & 0x3)); + SW(ed, wback, fixedaddress); + SMWRITE2(); + } + } + break; + case 0x18: + case 0x38: + if (opcode == 0x18) { + INST_NAME("VINSERTF128 Gx, Vx, Ex, imm8"); + } else { + INST_NAME("VINSERTI128 Gx, Vx, Ex, imm8"); + } + nextop = F8; + GETEX(x1, 1, 8); + GETGX(); + GETVX(); + GETGY(); + GETVY(); + u8 = F8; + if (u8 & 1) { + LD(x4, wback, fixedaddress + 0); + LD(x5, wback, fixedaddress + 8); + SD(x4, gback, gyoffset + 0); + SD(x5, gback, gyoffset + 8); + if (gd != vex.v) { + LD(x4, vback, vxoffset + 0); + LD(x5, vback, vxoffset + 8); + SD(x4, gback, gdoffset + 0); + SD(x5, gback, gdoffset + 8); + } + } else { + LD(x4, wback, fixedaddress + 0); + LD(x5, wback, fixedaddress + 8); + SD(x4, gback, gdoffset + 0); + SD(x5, gback, gdoffset + 8); + if (gd != vex.v) { + LD(x4, vback, vyoffset + 0); + LD(x5, vback, vyoffset + 8); + SD(x4, gback, gyoffset + 0); + SD(x5, gback, gyoffset + 8); + } + } + break; + case 0x19: + case 0x39: + if (opcode == 0x19) { + INST_NAME("VEXTRACTF128 Ex, Gx, imm8"); + } else { + INST_NAME("VEXTRACTI128 Ex, Gx, imm8"); + } + nextop = F8; + GETEX(x1, 1, 8); + GETGX(); + GETGY(); + u8 = F8; + if (u8 & 1) { + LD(x4, gback, gyoffset + 0); + LD(x5, gback, gyoffset + 8); + SD(x4, wback, fixedaddress + 0); + SD(x5, wback, fixedaddress + 8); + } else { + LD(x4, gback, gdoffset + 0); + LD(x5, gback, gdoffset + 8); + SD(x4, wback, fixedaddress + 0); + SD(x5, wback, fixedaddress + 8); + } + if (MODREG) { + YMM0(ed); + } else { + SMWRITE2(); + } + break; case 0x22: if (rex.w) { INST_NAME("VPINSRQ Gx, Vx, ED, Ib"); |