| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | [BUNDLE] Add script to bundle x86 libraries (#2380) | Luke Short | 2025-02-17 | 5 | -0/+212 | |
| | | | | | This manages both x86_64 and x86 libraries. It helps with improving emulation in all of the Box projects. | |||||
| * | [ARM64_DYNAREC] More work on UD flags | ptitSeb | 2025-02-17 | 6 | -158/+224 | |
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| * | [INTERP] Added more nops ([DYNAREC] too) (#2378) | Yang Liu | 2025-02-17 | 5 | -0/+5 | |
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| * | [INTERP] Added more nops ([DYNAREC] too) (#2377) | Yang Liu | 2025-02-17 | 4 | -1/+35 | |
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| * | [INTERP] Added 0F 19 NOP opcode ([DYNAREC] too) (#2376) | Yang Liu | 2025-02-17 | 4 | -0/+4 | |
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| * | [ARM64_DYNAREC] Continue work on UD flags | ptitSeb | 2025-02-17 | 9 | -397/+539 | |
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| * | [INTERP] Added 66 0F 19 NOP opcode ([DYNAREC] too) (#2375) | Yang Liu | 2025-02-17 | 5 | -1/+6 | |
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| * | [LA64_DYNAREC] Added more opcodes (#2374) | Yang Liu | 2025-02-17 | 3 | -8/+96 | |
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| * | [DYNAREC] Print decoded instruction mnemonics for missing opcodes if trace ↵ | Yang Liu | 2025-02-17 | 4 | -61/+65 | |
| | | | | | enabled (#2373) | |||||
| * | [ARM64_DYNAREC] Added more AVX opcodes (#2372) | wannacu | 2025-02-17 | 4 | -5/+84 | |
| | | | | | | * [ARM64_DYNAREC] Fixed AVX.F2.0F 12 opcode * [ARM64_DYNAREC] Added more AVX opcodes | |||||
| * | [LA64_DYNAREC] Minor optims and fixes to some opcodes (#2371) | Yang Liu | 2025-02-17 | 5 | -28/+127 | |
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| * | [LA64_DYNAREC] Added more SSE4 opcodes (#2370) | Yang Liu | 2025-02-17 | 1 | -0/+29 | |
| | | | | Co-authored-by: phorcys <phorcys@126.com> | |||||
| * | [LA64_DYNAREC] Added more opcodes (#2366) | Yang Liu | 2025-02-17 | 10 | -13/+330 | |
| | | | | | | * [LA64_DYNAREC] Added more opcodes * fix | |||||
| * | [ARM64_DYNAREC] Improved safeflags=2 | ptitSeb | 2025-02-16 | 9 | -107/+219 | |
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| * | [ARM64_DYNAREC] More work on UD flags | ptitSeb | 2025-02-15 | 4 | -239/+212 | |
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| * | [RCFILE] Added 1 more game profile | ptitSeb | 2025-02-15 | 1 | -0/+4 | |
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| * | [BOX64RC] Add Zenless Zone Zero Config (#2363) | Lily | 2025-02-15 | 1 | -0/+5 | |
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| * | [ARM64_DYNAREC] Add some opcodes (#2358) | wannacu | 2025-02-14 | 5 | -3/+167 | |
| | | | | | | | | | | | | * [ARM64_DYNAREC] Added 66 0F 3A 41 opcode * [ARM64_DYNAREC] Added AVX.66.0F38 DB opcode * [ARM64_DYNAREC] Added AVX.66.0F3A DF opcode * [ARM64_DYNAREC] Added AVX.F2.0F38 F5 opcode * [ARM64_DYNAREC] Added 66 F3 0F BC,B8 opcode | |||||
| * | [ARM64_DYNAREC] Fixed some issue with DF handling on mayset instructions | ptitSeb | 2025-02-13 | 1 | -12/+14 | |
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| * | [COSIM] Print decoded instruction mnemonics if trace enabled (#2357) | Yang Liu | 2025-02-13 | 1 | -8/+15 | |
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| * | [RV64_DYNAREC] Fixed F3 0F 11,12 opcodes for vector (#2356) | Yang Liu | 2025-02-13 | 1 | -2/+2 | |
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| * | [RV64_DYNAREC] Added a fastpath to SHL/SHR CL opcodes (#2355) | Yang Liu | 2025-02-13 | 1 | -1/+25 | |
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| * | [RV64_DYNAREC] Minor optimization to CMOV opcodes (#2354) | Yang Liu | 2025-02-13 | 1 | -5/+15 | |
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| * | [RV64_DYNAREC] Minor fixes and improvements to CMP opcodes (#2353) | Yang Liu | 2025-02-13 | 6 | -21/+26 | |
| | | | | | | * [RV64_DYNAREC] Minor fixes and improvements to CMP opcodes * review | |||||
| * | [ARM64_DYNAREC] The check on REP MOVSB overlapping memory is done with ↵ | ptitSeb | 2025-02-13 | 2 | -4/+28 | |
| | | | | | saflags=1 now | |||||
| * | [ARM64_DYNAREC] Added some BMI.0F38 opcodes (#2347) | wannacu | 2025-02-13 | 2 | -2/+113 | |
| | | | | | | | | | | * [ARM64_DYNAREC] Fixed BMI.0F38 F5 ocpode * [ARM64_DYNAREC] Added BMI.0F38 F3 /2,/3 ocpode * Added BMI.0F38 F7 opcode * Fixed emitter mistake about CSINVxw | |||||
| * | [RV64_DYNAREC] Minor fixes and improvements to TEST opcodes (#2352) | Yang Liu | 2025-02-13 | 3 | -14/+61 | |
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| * | [ARM64_DYNAREC] Small optims to AVX.66.0F38 16/18/19/36 opcodes | ptitSeb | 2025-02-13 | 1 | -19/+17 | |
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| * | [ARM64_DYNAREC] Fixed LD1R and CBN/CBNZ printer | ptitSeb | 2025-02-13 | 1 | -10/+8 | |
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| * | [ARM64_DYNAREC] Fixed regression introduced with ↵ | ptitSeb | 2025-02-13 | 1 | -27/+36 | |
| | | | | | b8cc8594f6d9cbe4a47b8a98ba9878da803a7243 | |||||
| * | [RCFILE] Added 2 more game profiles | ptitSeb | 2025-02-12 | 1 | -0/+13 | |
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| * | [ARM64_DYNAREC] Fixed some issue with DF and mayset opcodes | ptitSeb | 2025-02-12 | 1 | -3/+5 | |
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| * | [COSIM] Added commented way to dumps regs whe printing a difference | ptitSeb | 2025-02-12 | 1 | -0/+1 | |
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| * | Limit to 11 the number of cpuid invalid parameter message | ptitSeb | 2025-02-12 | 1 | -1/+7 | |
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| * | [ARM64_DYNAREC] Removed obsolete comment | ptitSeb | 2025-02-12 | 1 | -1/+1 | |
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| * | [ARM64_DYNAREC] Improved some 66 F0 opcode, especially unaligned path | ptitSeb | 2025-02-12 | 2 | -17/+30 | |
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| * | [RCFILE] Added 2 game profiles | ptitSeb | 2025-02-12 | 1 | -0/+14 | |
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| * | [ARM64_DYNAREC] Improved many LOCK prefixed opcodes, espcialy unaligned path | ptitSeb | 2025-02-12 | 4 | -104/+211 | |
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| * | [ARM64_DYNAREC] More work on flag | ptitSeb | 2025-02-12 | 8 | -605/+472 | |
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| * | fix VPMASKMOV and VMASKMOVP (#2342) | ye-yeshun | 2025-02-12 | 2 | -68/+459 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * fix: 0x2C: 'VMASKMOVPS Gx, Vx, Ex' Log: VMASKMOVPS读取内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: I197fc356edcac202b5a329c50c334d0166532e93 * fix: 0x2D: 'VMASKMOVPD Gx, Vx, Ex' Log: VMASKMOVPD读取内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: Ie11d93971aa92b141540a37bfdae0b3b060e3aea * fix: 0x2E: 'VMASKMOVPS Ex, Gx, Vx' Log: VMASKMOVPS写入内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: Ide5cb36dc03fc56480fdd45e7d96daed8557d849 * fix: 0x2F: 'VMASKMOVPD Ex, Gx, Vx' Log: VMASKMOVPD写入内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: I037de8568e9d2d29597fdf08f991d54e3cb2f6d9 * fix: 0x8E: 'VPMASKMOVD/Q Ex, Vx, Gx' Log: VPMASKMOVD/Q写入内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: I0dc98a29ed933d953e137e777bc296149d94b10b * tests: add test for VPMASKMOV and VMASKMOVP Log: Signed-off-by: YeshunYe <yeyeshun@uniontech.com> --------- Signed-off-by: YeshunYe <yeyeshun@uniontech.com> | |||||
| * | [RCFILE] Improved support for windows setup | ptitSeb | 2025-02-12 | 2 | -3/+1 | |
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| * | [ARM64_DYNAREC] Fixed F0 0F B1 ocpode (emit_cmp32 can only be used once per ↵ | ptitSeb | 2025-02-11 | 1 | -10/+13 | |
| | | | | | opcode, because of the df flags handling) | |||||
| * | [ARM64_DYNAREC] Fixed wrong COUNT operand in VPSLL{W,D,Q} (#2344) | wannacu | 2025-02-11 | 1 | -12/+15 | |
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| * | [LA64_DYNAREC] Added F3 0F 52 RSQRTSS opcode (#2343) | Yang Liu | 2025-02-11 | 1 | -0/+13 | |
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| * | [ARM64_DYNAREC] Added code on safeflags=2 to check if SI/DI memory overlap ↵ | ptitSeb | 2025-02-11 | 2 | -1/+15 | |
| | | | | | on fast rep movsb opcode | |||||
| * | [LA64_DYNAREC] Added F2 0F 7D HSUBPS opcode (#2341) | Yang Liu | 2025-02-11 | 1 | -0/+11 | |
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| * | [ARM64_DYNAREC] Some changes on shift opcode and OF handling, and added some ↵ | ptitSeb | 2025-02-10 | 2 | -31/+60 | |
| | | | | | new profiles | |||||
| * | [ARM64_DYNAREC] Mostly cosmetic change on (I)DIV 8bits opcode | ptitSeb | 2025-02-10 | 1 | -35/+31 | |
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| * | [LA64_DYNAREC] Added preliminary optimization for REP MOVSB (#2340) | Yang Liu | 2025-02-10 | 2 | -0/+28 | |
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| * | [LA64_DYNAREC] Added more opcodes (#2339) | Yang Liu | 2025-02-10 | 6 | -2/+204 | |
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