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* [RV64_DYNAREC] Small optimization to LEA opcode (#2582)Yang Liu2025-04-283-8/+9
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* [ARM64_DYNAREC] Mostly cosmetic changes to SSE/AVX packed shift opcodesptitSeb2025-04-282-43/+37
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* [INTERP] Fixes and improvments to SSE/AVX packed shift opcodesptitSeb2025-04-283-84/+40
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* [RV64_DYNAREC] Optimized rv64 printer for pseudo and jump instructions (#2581)Yang Liu2025-04-281-7/+55
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* Show Dynarec architecture in version string (#2580)Yang Liu2025-04-283-34/+43
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* [RV64_DYNAREC] Minor adjustment to dynarec_missing=2 (#2578)Yang Liu2025-04-283-4/+4
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* [ARM64_DYNAREC] Small optim for PSIGN[B/W/D] opcodesptitSeb2025-04-272-33/+27
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* [ARM64_DYNAREC] Some work on UD flags on (66) F3 0F BC/BD opcodesptitSeb2025-04-272-16/+64
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* [ARM64_DYNAREC] More work on UD flags for (66) F3 0F BC/BD opcodesptitSeb2025-04-272-4/+60
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* [ARM64_DYNAREC] Minor fox to F6 /7 opcodeptitSeb2025-04-271-1/+1
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* [INTERP] More work on UD flagsptitSeb2025-04-275-13/+65
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* [INTERP] Fixed some potential issue with LOCK ADC/SBB on Dynarec buildptitSeb2025-04-271-15/+23
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* [INTERP] Added 66 F3 0F BC opcodeptitSeb2025-04-271-0/+33
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* [WRAPPER] Reworked libssh2 wrapping, to make it more completeptitSeb2025-04-277-7/+418
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* [WRAPPERHELPER] Fixed a small issue with the parserptitSeb2025-04-271-1/+1
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* [ELFLOADER] Fixed an issue were fail to load a library might endup unloading ↵ptitSeb2025-04-271-6/+0
| | | | used libraries
* [ELFLOADER] Added lib loading/unloading logs to DLSYM_ERRORptitSeb2025-04-272-6/+13
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* [RCFILE] Fixed BOX64_ROLLING_LOG not being a boolean but an integer valueptitSeb2025-04-271-1/+1
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* [ARM64_DYNAREC] Refactored (V)PSHUFD opcodesptitSeb2025-04-262-111/+183
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* [INTERP] Cosmetic change to VPSHUFD opocdeptitSeb2025-04-261-1/+1
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* [WRAPPER] Fixed some potential sagfault on my_backtrace wrapped functionptitSeb2025-04-261-0/+6
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* [ARM64_DYNAREC] Allow shift with saturation on (V)PMULH(U)W because it will ↵ptitSeb2025-04-263-10/+5
| | | | never saturate
* [ARM64_DYNAREC] Small fix for edge cases on (V)PMULHUW opcodesptitSeb2025-04-263-8/+10
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* [WRAPPER] Added some missing function to wrapped libgio-2 (for #2575)ptitSeb2025-04-267-2/+34
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* [ARM64_DYNAREC] Fixed (rarely used) some edge case for (V)PMULHRSW opcode ↵ptitSeb2025-04-2511-7/+84
| | | | (and improved tests)
* [ARM64_DYNAREC] Small optim on some 256bits VPMOV[S/Z]X* opcodesptitSeb2025-04-251-22/+14
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* [ARM64_DYNAREC] Allow bigger block to be builtptitSeb2025-04-252-3/+5
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* [ARM64_DYNAREC] Minor change, (V)PMOVMSKB is only valid on register, not memoryptitSeb2025-04-252-39/+47
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* [INTERP] Another fix for a opcode name in commentptitSeb2025-04-251-1/+1
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* [INTERP] Fixed a small issue where VPCMP[E/I]STRM would not wipe upper ↵ptitSeb2025-04-251-2/+2
| | | | 128bits of ymm0
* [ARM64_DYNAREC] Fixed a potential issue with PCMPEQQ opcodes, and many ↵ptitSeb2025-04-251-63/+63
| | | | missing space in instruction name
* [ARM64_DYNAREC] Improved and fixed software fallback for (V)PCLMULQDQ opcodesptitSeb2025-04-242-37/+24
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* [ARM64_DYNAREC] Some optimisation to some (V)(P)BLEND* opcodesptitSeb2025-04-242-63/+21
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* [INTERP] Yet another opcode name comment fixptitSeb2025-04-241-1/+1
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* [SIGNAL] Better signal logging when trace enabled (#2572)Yang Liu2025-04-241-2/+11
| | | | | * [SIGNAL] Better signal logging when trace enabled * fix
* [RV64_DYNAREC] Fixed x87 cache swapping (#2571)Yang Liu2025-04-242-9/+11
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* [ARM64_DYNAREC] Small optim on (V)PACKUSDW opcodesptitSeb2025-04-242-14/+4
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* [LA64_DYNAREC] Add/Opt more mmx/sse ops (#2565)phorcys2025-04-242-46/+180
| | | | | | | | | | | | | | | * [LA64_DYNAREC] Add/Opt PEXTR{B,W,D,Q}/PINSR{B,W,D,Q} . * 0f.c4/c5 PINSRW/PEXTRW mmx ops. * 66.0f.3a.14/15/16 PEXTR{B,W,D/Q} SSE4 ops. * 66.0f.c4/c5 PINSRW/PEXTRW sse ops. * [LA64_DYNAREC] Add more SSE3/SSE4 ops 66.0f.38.28 PMULDQ 66.0f.38.2a MOVNTDQA 66.0f.38.37 PCMPGTQ 66.0f.38.38/3b/3c/3f PMINSB/PMINUD/PMAXSB/PMAXUD 66.0f.3a.17 EXTRACTPS 66.0f.3a.41 DPPD opt 66.0f.3a.40 DPPS
* [INTERP] Cosmetic change to 0F 1C..1E opcodesptitSeb2025-04-241-3/+3
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* [INTERP] Added nan handling on AVX.F3.0F 59 opcodeptitSeb2025-04-241-0/+2
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* [ARM64_DYNAREC] Simplified code for MOVS[H/L]DUP opcodesptitSeb2025-04-242-19/+3
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* [INTERP] Fixed another opcode name commentptitSeb2025-04-241-1/+1
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* [LA64_DYNAREC] Add POPCNT/TZCNT/LZCNT ops. (#2566)phorcys2025-04-246-8/+171
| | | | | 66.f3.0f.b8/bc/bd POPCNT/TZCNT/LZCNT 16bits ops f3.0f.bd LZCNT fix f3.0f.bc TZCNT (GETED/RESTORE_EFLAGS x1 conflict)
* [ARM64_DYNAREC] Small iùprovments to some (V)MOVQ opcodesptitSeb2025-04-244-11/+12
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* [INTERP] Fixed a commentptitSeb2025-04-241-1/+1
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* [ARM64_DYNAREC] Small change and optims to various (V)MOVNT* opcodesptitSeb2025-04-244-33/+24
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* [INTERP] Small change to various (V)MOVNT* opcodes, forbidding reg -> reg formptitSeb2025-04-246-56/+74
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* [DYNAREC] Added ranged Dynablock dump (#2570)Yang Liu2025-04-2426-114/+141
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* [ARM64_DYNAREC] Minor optim to MOVNTDQA (#2568)Yang Liu2025-04-241-3/+10
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* Added some missing newlines (#2567)Yang Liu2025-04-241-2/+2
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