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* [INTERP] Try to improve aligned LOCK CMPXCHG8B opcodeptitSeb2025-08-011-0/+25
* [DYNACACHE] Refactored cpu extension, will be used in dynacache signature checksptitSeb2025-06-141-31/+31
* [ARM64] Use crc32 hardware support (if available) for dynablock signatureptitSeb2025-03-311-0/+22
* [ARM64_DYNAREC] Added atomic support for various lock helpersptitSeb2025-03-301-0/+120
* [DYNAREC] Changed lock mecanism for memory protectionptitSeb2023-10-011-0/+15
* [DYNAREC] Small improvment on multi-thread reliance for the jumptableptitSeb2023-09-091-0/+6
* remove executable bitsJohannes Schauer Marin Rodrigues2023-07-211-0/+0
* [ARM64_DYNAREC] Fixed buildptitSeb2023-03-121-1/+23
* [DYNAREC] Some renaming for the sake of consistancyptitSeb2023-03-121-3/+3
* [DYNAREC] Simplify arm64 lock fileYang Liu2023-03-101-32/+32
* [DYNAREC] More small fixes to arm64 lock fileptitSeb2023-03-091-12/+1
* [ARM64] Fixed a typo in arm64_lock_incif0Yang Liu2023-03-091-1/+1
* [DYNAREC] Use custom mutex, improved Signal while FillBlocks64 and atomic han...ptitSeb2023-02-121-4/+49
* [DYNAREC] Reworked dynarec memory allocator, and a bit of protection tracking...ptitSeb2022-12-031-0/+37
* [DYNAREC] Optimized HotPage handling, and made it locklessptitSeb2022-11-281-1/+21
* Made a custom implementation of pthread_onceptitSeb2022-10-261-0/+12
* [DYNAREC] Refactored dynarec to ease the future adding of new target architec...ptitSeb2022-02-271-0/+131