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* [ARM64_DYNAREC] Small adjustement to 2 AVX opcodesptitSeb2025-04-041-3/+3
* [LA64_DYNAREC] Optimize la64 MAXPD/MAXPS. (#2499)phorcys2025-04-032-8/+4
* Decoupled alternate functions from bridge (#2500)Yang Liu2025-04-035-1/+5
* Moved more functions to os.h (#2497)Yang Liu2025-04-0397-119/+23
* [ARM64_DYNAREC] Removed some condition on vex.l that shouldn't be here on a f...ptitSeb2025-04-032-6/+6
* [LA64_DYNAREC] Add more sse ops (#2493)phorcys2025-04-034-32/+283
* [ARM64_DYNAREC] Small optim for VBLENDPS opcodeptitSeb2025-04-021-6/+14
* [ARM64_DYNAREC] Fixed an optim in BLENDPS opcodeptitSeb2025-04-021-2/+2
* Moved some emit functions to os.h (#2494)Yang Liu2025-04-022-12/+7
* Moved more OS-dependent functions to os.h (#2491)Yang Liu2025-04-012-18/+7
* Introduced box64cpu.h for exported interpreter and dynarec functions (#2490)Yang Liu2025-04-01109-215/+109
* [LA64_DYNAREC] Fix f0.80.1 LOCK OR, LoongArch ANDI is zero-extended. (#2489)phorcys2025-04-011-1/+2
* Added os.h for future usage (#2488)Yang Liu2025-04-013-0/+3
* Some cosmetic changes to C header files (#2487)Yang Liu2025-04-017-35/+5
* [ARM64] Use crc32 hardware support (if available) for dynablock signatureptitSeb2025-03-313-0/+28
* [ARM64_DYNAREC] Added atomic support for various lock helpersptitSeb2025-03-302-0/+129
* [RV64] Improved rv64_lock_cas[b/h] helpersptitSeb2025-03-301-2/+2
* [LA64] Fixed la64_lock_cas_[h/b]_slow helper (rarely used)ptitSeb2025-03-301-2/+2
* [ARM64_DYNAREC] Fixed a potential issue with SSE regs when internal jumping t...ptitSeb2025-03-292-3/+24
* [LA64_DYNAREC] Added more MMX opcodes (#2479)Yang Liu2025-03-281-70/+233
* [LA64_DYNAREC] Added more MMX opcodes (#2477)Yang Liu2025-03-284-0/+125
* [LA64_DYNAREC] Added preliminary MMX support (#2476)Yang Liu2025-03-286-45/+200
* [LA64_DYNAREC] Added more opcodes (#2475)Yang Liu2025-03-281-26/+76
* [LA64_DYNAREC] Added more opcodes (#2473)Yang Liu2025-03-271-0/+71
* [LA64_DYNAREC] Added more opcodes (#2472)Yang Liu2025-03-271-0/+30
* [ARM64_DYNAREC] Added fastnan=0 path for HSUBPS opcodeptitSeb2025-03-261-0/+13
* [ARM64_DYNAREC] Improved VHSUBPS opcode, and added fastnan=0 pathptitSeb2025-03-261-13/+16
* [ARM64_DYNAREC] Commented a message that doesn't seems releventptitSeb2025-03-261-2/+2
* [COSIM] Changed how F0 LOCK opcodes are skipped in COSIMptitSeb2025-03-261-1/+1
* [ARM64_DYNAREC] Improved (V)HADDPS with fastnan=0ptitSeb2025-03-262-4/+39
* [ARM64_DYNAREC] Addedfastnan=0 code to (V)SQRTPS opcodesptitSeb2025-03-262-4/+30
* [ARM64_DYNAREC] Improved (V)MAXP[S/D] and (V)MINP[S/D] opcodes to more closel...ptitSeb2025-03-264-40/+47
* [ARM64_DYNAREC] Small change on AVX.66.0F38 BA opcode to more closely match x...ptitSeb2025-03-261-3/+11
* [RV64_DYNAREC] Fixed 66 0F 6A PUNPCKHDQ opcodes (#2468)Yang Liu2025-03-261-2/+2
* [RV64_DYNAREC] Minor improvement to DD /7 FNSTSW opcode (#2467)Yang Liu2025-03-251-0/+1
* [RV64_DYNAREC] Fixed D9 E5 FXAM opcode (#2466)Yang Liu2025-03-251-3/+3
* [RV64_DYNAREC] Small optim to vsetvli usage (#2465)Yang Liu2025-03-251-1/+3
* [RV64_DYNAREC] Fixed scratch conflicts with fastround=0 in some x87 opcodes (...Yang Liu2025-03-245-14/+11
* [RV64_DYNAREC] Fixed some DD prefixed x87 opcodes (#2463)Yang Liu2025-03-241-2/+10
* [DYNAREC] Better handling of blocksize limit when generating very large dynab...ptitSeb2025-03-243-13/+27
* [ARM64_DYNAREC] Better log for arch_populate buffer being undersizedptitSeb2025-03-221-3/+2
* [ARM64_DYNAREC] Fixed potential issue on unligned path being marked while dyn...ptitSeb2025-03-222-4/+4
* [ARM64_DYNAREC][TRACE] Added a message on Dump for Unaligned path on opcodesptitSeb2025-03-225-0/+7
* [ARM64_DYNAREC] Added 67 66 0F 76/EF opcodes (for #1046)ptitSeb2025-03-211-1/+36
* [RV64_DYNAREC] Fixed many minor issues (#2451)Yang Liu2025-03-196-60/+65
* [DYNAREC] Fixed minor issues for F0 0F B0/B1 LOCK CMPXCHG opcodes (#2448)Yang Liu2025-03-193-24/+20
* [RV64_DYNAREC] Added 66 F0 0F B1 LOCK CMPXCHG opcode (#2447)Yang Liu2025-03-181-0/+53
* [RV64_DYNAREC] More minor changes and fixes to x87 opcodes (#2443)Yang Liu2025-03-175-91/+63
* [DYNAREC] Small change in strongmem to end a SEQ with a Brrier at last_write ...ptitSeb2025-03-171-2/+3
* [DYNAREC] Change in strongmem managment to end a SEQ on jump arrival and not ...ptitSeb2025-03-171-1/+1