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2025-07-01Simplified a bit ROLLING_LOG buffer handlingptitSeb5-23/+15
2025-07-01[ARM64_DYNAREC] Optimized propate XMM/YMM unused helpersptitSeb1-26/+11
2025-06-30[ARM64_DYNAREC] Fixed a regression introduced with 4903177bab1f3324a0faeedd96...ptitSeb1-1/+1
2025-06-30[DYNAREC] Refactor hotpage detection and dynarec_dirty 1 & 2. Also adjust som...ptitSeb8-52/+256
2025-06-29[ARM64_DYNAREC] Added 66 8D opcodeptitSeb1-1/+16
2025-06-29[ARM64_DYNAREC] Added 67 9C opcodeptitSeb1-0/+6
2025-06-29[ARM64_DYNAREC] Made (V)M(IN/AX)P(D/S) opcodes always exact, it's inexpensive...ptitSeb3-38/+16
2025-06-28[INTERP] Added 67 9C opcode (for LEGO2Kdrive)ptitSeb1-0/+6
2025-06-28[INTERP] Small imrpvoment for 0F 03 opcodeptitSeb1-1/+1
2025-06-28[INTERP] Added 0F 03 opcode (for LEGO2Kdrive)ptitSeb1-0/+14
2025-06-28[ARM64_DYNAREC] Use Unaligned sepcial handling to handle rare case of 32bits ...ptitSeb1-4/+21
2025-06-27[LA64_DYNAREC] Removed some TABLE64 usage (#2782)Yang Liu1-21/+12
2025-06-27[LA64_DYNAREC] Add la64 avx load/store ops part 4. (#2775)phorcys1-0/+252
2025-06-27[LA64_DYNAREC] Optimized GETIP macro (#2781)Yang Liu6-51/+49
2025-06-26[LA64_DYNAREC] Removed some redundant macro definitions (#2778)Yang Liu1-2/+0
2025-06-26[DYNACACHE][LA64] More work on internal reloc (#2779)Yang Liu5-13/+23
2025-06-26[LA64_DYNAREC] Add la64 avx load/store ops part 3. (#2774)phorcys6-10/+416
2025-06-26[LA64_DYNAREC] Add la64 avx load/store ops part 2. (#2773)phorcys2-0/+113
2025-06-25[ARM64_DYNAREC] Fixed opcode name for VDIVPDptitSeb1-1/+1
2025-06-25[ARM64_DYNAREC] Fixed some extended instance of VCMPSD opcodesptitSeb1-3/+3
2025-06-25[INTERP] Improved 32bits to 16bits float conversionptitSeb1-6/+21
2025-06-25[INTERP] More work on UD flagsptitSeb1-5/+17
2025-06-25[INTERP] More work on UD flagsptitSeb1-6/+11
2025-06-25[ARM64_DYNAREC] Adjusted some UD flags in BLSMSK opcodeptitSeb1-4/+14
2025-06-25[INTERP] Adjusted some UD flags in BLSMSK opcodeptitSeb1-4/+18
2025-06-25[ARM64_DYNAREC] Fixed CF flag of BLSI opcodeptitSeb1-1/+1
2025-06-25[INTERP] Fixed CF flag of BLSI opcodeptitSeb1-1/+1
2025-06-25[ARM64_DYNAREC] Fixed BEXTR opcodeptitSeb1-11/+13
2025-06-24[INTERP] Added 66 F0 F7 /2 opcode (aligned only)ptitSeb2-1/+36
2025-06-24[ARM64_DYNAREC] Improved BTx opcodes (and fixed one BTC opcode)ptitSeb1-41/+141
2025-06-24[INTERP] Added F0 BB and improved F0 BA /7 opcodesptitSeb1-9/+94
2025-06-24[DYNAREC] Better check of limit for a dynablockptitSeb2-2/+2
2025-06-24[WRAPPER] additional wrapped symbols (#2765)airidosas2522-0/+16
2025-06-24[LA64_DYNAREC] Add la64 avx load/store ops part 1. (#2766)phorcys5-12/+194
2025-06-24[ARM64_DYNAREC] Improved handling of last_ipptitSeb5-2/+5
2025-06-24[DYNACACHE][LA64] Added const table for later use in internal relocation (#2770)Yang Liu13-69/+318
2025-06-24[LA64_DYNAREC] This should help certain builds (for #2769)ptitSeb2-5/+10
2025-06-24[CI] Upgraded QEMU and loongarch64 toolchains (#2768)Yang Liu1-4/+6
2025-06-24[DYNAREC] Removed some unused code (#2767)Yang Liu6-26/+0
2025-06-23[LA64_DYNAREC]Add basic avx support for la64. (#2745)phorcys16-70/+5585
2025-06-23Fix wowbox64 buildptitSeb1-0/+12
2025-06-23[DYNACACHE] Added support for unaligned addressesptitSeb2-4/+49
2025-06-23[ARM64_DYNAREC] Removed commented codeptitSeb1-1/+0
2025-06-23Add `map64_customMalloc` (#2764)Chi-Kuan Chiu1-6/+140
2025-06-23[DYNAREC] Refactored a bit BARRIER_FLOAT ([ARM64] olny for now, todo for RV64...ptitSeb16-42/+118
2025-06-22[ARM64_DYNAREC] Small fix in arch_buildptitSeb1-1/+1
2025-06-20[DYNACACHE] Introduced B64X_DYNACACHE=2 to use cache but not create new ones,...ptitSeb5-15/+19
2025-06-20[DYNACACHE] Fixed a WarningptitSeb1-1/+1
2025-06-20[DYNACACHE][RV64] Enabled dynacache for RV64 (#2762)Yang Liu7-60/+119
2025-06-20[DYNACACHE] Make sure dynacache folder ends with pathsep (#2761)Yang Liu1-29/+29