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* [ARM64_DYNAREC] Fixed VCMPSS opcodeptitSeb2024-06-061-0/+50
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* Wrapped libtasn1-6 (#1563)LiZhuoheng2024-06-069-0/+103
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* Wrapped libp11-kit (#1562)LiZhuoheng2024-06-067-0/+80
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* [ARM64_DYNAREC] Added a few more AVX opcodesptitSeb2024-06-055-8/+138
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* [ARM64_DYNAREC] Added a bunch of AVX ocpodes and some fixes tooptitSeb2024-06-058-89/+301
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* [INTERPRETER] Fixed VCMP opcode familly, that needs more cases on than ↵ptitSeb2024-06-054-55/+116
| | | | con-vex CMP familly
* [DYNAREC] Improved handling of the Ymm0 attributeptitSeb2024-06-0511-25/+69
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* [ARM64_DYNAREC] Small optim for AVX.66.0F D7 opcodeptitSeb2024-06-051-23/+19
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* [LA64_DYNAREC] Fixed LOCK DEC opcode (#1560)Yang Liu2024-06-041-1/+1
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* [DYNAREC] Small improvment to Dynarec infrastructureptitSeb2024-06-041-1/+4
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* [ARM64_DYNAREC] Added AVX.0F 16/50/53/C2 opcodesptitSeb2024-06-031-1/+113
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* [LA64_DYNAREC] Added more opcodes (#1558)Yang Liu2024-06-0310-2/+447
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* [LA64_DYNAREC] Fixed emit_or16 (#1559)Yang Liu2024-06-031-1/+1
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* [ARM64_DYNAREC] Added AVX.66.0F 5A/5C-5F/D0-D3ptitSeb2024-06-031-2/+183
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* [ARM64_DYNAREC] Cosmetic changeptitSeb2024-06-031-10/+10
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* [ARM64_DYNAREC] Added AVX.66.0F3A 02/08-09/0E/14/20/40/4A-4B opcodesptitSeb2024-06-032-0/+200
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* [INTERPRETER] Fixed name in comment of an opcodeptitSeb2024-06-031-2/+2
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* [RV64_DYNAREC] Added more MMX opcodes and some optimizations too (#1557)xctan2024-06-032-19/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Added 0F 38 0B PMULHRSW opcode * [RV64_DYNAREC] Added 0F E4 PMULHUW opcode * [RV64_DYNAREC] Added 0F F4 PMULUDQ opcode * [RV64_DYNAREC] Added 0F F6 PSADBW opcode * [RV64_DYNAREC] Added 0F 38 08 PSIGNB opcode * [RV64_DYNAREC] Optimized 66 0F 38 08 PSIGNB opcode * [RV64_DYNAREC] Added 0F 38 0A PSIGND opcode * [RV64_DYNAREC] Optimized 66 0F 38 0A PSIGND opcode * [RV64_DYNAREC] Added 0F 38 09 PSIGNW opcode * [RV64_DYNAREC] Optimized 66 0F 38 09 PSIGNW opcode * [RV64_DYNAREC] Added 0F F2 PSLLD opcode * [RV64_DYNAREC] Added 0F F3 PSLLQ opcode * [RV64_DYNAREC] Added 0F F1 PSLLW opcode * [RV64_DYNAREC] Fixed 0F F1/F2 PSLLW/PSLLD opcode * [RV64_DYNAREC] Added 0F E1 PSRAW opcode * [RV64_DYNAREC] Added 0F D2 PSRLD opcode * [RV64_DYNAREC] Added 0F D3 PSRLQ opcode * [RV64_DYNAREC] Added 0F D1 PSRLW opcode * [RV64_DYNAREC] Added 0F F8 PSUBB opcode * [RV64_DYNAREC] Added 0F FA PSUBD opcode * [RV64_DYNAREC] Added 0F FB PSUBQ opcode * [RV64_DYNAREC] Added 0F E8 PSUBSB opcode and optimized 0F E9 PSUBSW opcode * [RV64_DYNAREC] Added 0F D8 PSUBUSB opcode
* [ARM64_DYNAREC] Added AVX.66.0F38 ↵ptitSeb2024-06-033-2/+503
| | | | 17/20-25/29/37-40/45-47/78-79/99/AA/AE-AF/BB-BD/F7 opcodes
* [INTERPRETER] Fixed name in comment of an opcodeptitSeb2024-06-031-1/+1
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* [ARM64_DYNAREC] Added AVX.66.0F38 19/1A and AVX.66.0F3A 22 opcodesptitSeb2024-06-032-0/+44
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* [ARM64_DYNAREC] Fixed AVX.F2/F3.0F 5D/5F opcodesptitSeb2024-06-032-18/+10
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* [ARM64_DYNAREC] Empty regs needs to be fetched last (again)ptitSeb2024-06-031-42/+14
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* [ARM64_DYNAREC] Fixed AVX Cache transform between internal jump pointsptitSeb2024-06-032-5/+7
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* [COSIM] Added more helpers to avoid segfault on rare casesptitSeb2024-06-034-8/+11
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* [ARM64_DYNAREC] Empty register needs to be fetched lastptitSeb2024-06-031-17/+9
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* [INTERPRETER] Fixed VZEROUPPER opcodeptitSeb2024-06-031-1/+1
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* Try to fix mmap64 already defined error in custommem.c (#1552)Romain TISSERAND2024-06-032-26/+49
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* [ARM64_DYNAREC] Added AVX.F3.0F 52, AVX.66.0F E4 and AVX.0F 52 opcodesptitSeb2024-06-023-0/+59
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* [ARM64_DYNAREC] Added AVX.66.0F38 08-0A/1C-1E/30-35/58/59/90/92/A8/A9/B8/B9 ↵ptitSeb2024-06-024-5/+366
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* [ARM64_DYNAREC] Remove parasite typo to fix buildptitSeb2024-06-021-1/+1
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* [INTERPRETER] Added missing FMA opcodes, and fixed some existing onesptitSeb2024-06-021-12/+156
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* [INTERPRETER] Fixed opcode name in commentptitSeb2024-06-021-3/+3
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* [ARM64_DYNAREC] Added AVX.66.0F D6/E5/E7/F5 opcodesptitSeb2024-06-021-1/+66
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* [ARM64_DYNAREC] Added AVX.66.0F3A 00/01/04/05/0A/0B/46 opcodesptitSeb2024-06-021-0/+126
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* [ARM64_DYNAREC] Fixed handling of YMM0 on forward jumpptitSeb2024-06-023-3/+7
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* [COSIM] Fixed YMM handling in cosim, seems to work better nowptitSeb2024-06-023-1/+16
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* [ARM64_DYNAREC] Added AVX.66.0F 60-63/67-6A/71 opcodesptitSeb2024-06-021-4/+163
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* [ARM64_DYNAREC] Don't use fix scratch for x87 conversion, it might conflict ↵ptitSeb2024-06-023-17/+36
| | | | with YMM handling
* [INTERPRETER] Small cosmetic changes on raz of ymmptitSeb2024-06-021-9/+9
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* [COSIM] Improved reliability with AVX (but there is still something wrong there)ptitSeb2024-06-022-14/+15
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* [INTERPRETER] Added FMA cpu extension (linked to BOX64_AVX=2)ptitSeb2024-06-023-2/+449
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* [ARM64_DYNAREC] Fixed YMM COSIM refreshing on each stepsptitSeb2024-06-021-3/+3
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* [COSIM] Fixed issue with YMM printing on differenceptitSeb2024-06-021-1/+1
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* [LA64_DYNAREC] Added more opcodes (#1549)Yang Liu2024-06-029-0/+654
| | | | | * [LA64_DYNAREC] Added more opcodes * fastnan handling and fixed PALIGNR...
* [ARM64_DYNAREC] Added AVX.66.0F3A 21 and fixed a bunch of issuesptitSeb2024-06-025-21/+62
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* [INTERPRETER] Small fixes for some rare case of AES with serc==destptitSeb2024-06-021-19/+19
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* [LA64_DYNAREC] Added more opcodes and fixed ADC opcode (#1548)Yang Liu2024-06-013-19/+67
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* [ARM64_DYNAREC] Added AVX.F2.0F 58-5A/5C-5F opcodesptitSeb2024-06-011-0/+123
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* [ARM64_DYNAREC] Added AVX.66.0F C4/C5/D7 opcodesptitSeb2024-06-012-0/+81
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