about summary refs log tree commit diff stats
path: root/src (follow)
Commit message (Collapse)AuthorAgeFilesLines
...
* [ARM64_DYNAREC] More work on UD flagsptitSeb2025-02-154-239/+212
|
* [ARM64_DYNAREC] Add some opcodes (#2358)wannacu2025-02-145-3/+167
| | | | | | | | | | | * [ARM64_DYNAREC] Added 66 0F 3A 41 opcode * [ARM64_DYNAREC] Added AVX.66.0F38 DB opcode * [ARM64_DYNAREC] Added AVX.66.0F3A DF opcode * [ARM64_DYNAREC] Added AVX.F2.0F38 F5 opcode * [ARM64_DYNAREC] Added 66 F3 0F BC,B8 opcode
* [ARM64_DYNAREC] Fixed some issue with DF handling on mayset instructionsptitSeb2025-02-131-12/+14
|
* [COSIM] Print decoded instruction mnemonics if trace enabled (#2357)Yang Liu2025-02-131-8/+15
|
* [RV64_DYNAREC] Fixed F3 0F 11,12 opcodes for vector (#2356)Yang Liu2025-02-131-2/+2
|
* [RV64_DYNAREC] Added a fastpath to SHL/SHR CL opcodes (#2355)Yang Liu2025-02-131-1/+25
|
* [RV64_DYNAREC] Minor optimization to CMOV opcodes (#2354)Yang Liu2025-02-131-5/+15
|
* [RV64_DYNAREC] Minor fixes and improvements to CMP opcodes (#2353)Yang Liu2025-02-136-21/+26
| | | | | * [RV64_DYNAREC] Minor fixes and improvements to CMP opcodes * review
* [ARM64_DYNAREC] The check on REP MOVSB overlapping memory is done with ↵ptitSeb2025-02-132-4/+28
| | | | saflags=1 now
* [ARM64_DYNAREC] Added some BMI.0F38 opcodes (#2347)wannacu2025-02-132-2/+113
| | | | | | | | | * [ARM64_DYNAREC] Fixed BMI.0F38 F5 ocpode * [ARM64_DYNAREC] Added BMI.0F38 F3 /2,/3 ocpode * Added BMI.0F38 F7 opcode * Fixed emitter mistake about CSINVxw
* [RV64_DYNAREC] Minor fixes and improvements to TEST opcodes (#2352)Yang Liu2025-02-133-14/+61
|
* [ARM64_DYNAREC] Small optims to AVX.66.0F38 16/18/19/36 opcodesptitSeb2025-02-131-19/+17
|
* [ARM64_DYNAREC] Fixed LD1R and CBN/CBNZ printerptitSeb2025-02-131-10/+8
|
* [ARM64_DYNAREC] Fixed regression introduced with ↵ptitSeb2025-02-131-27/+36
| | | | b8cc8594f6d9cbe4a47b8a98ba9878da803a7243
* [ARM64_DYNAREC] Fixed some issue with DF and mayset opcodesptitSeb2025-02-121-3/+5
|
* [COSIM] Added commented way to dumps regs whe printing a differenceptitSeb2025-02-121-0/+1
|
* Limit to 11 the number of cpuid invalid parameter messageptitSeb2025-02-121-1/+7
|
* [ARM64_DYNAREC] Removed obsolete commentptitSeb2025-02-121-1/+1
|
* [ARM64_DYNAREC] Improved some 66 F0 opcode, especially unaligned pathptitSeb2025-02-122-17/+30
|
* [ARM64_DYNAREC] Improved many LOCK prefixed opcodes, espcialy unaligned pathptitSeb2025-02-124-104/+211
|
* [ARM64_DYNAREC] More work on flagptitSeb2025-02-128-605/+472
|
* fix VPMASKMOV and VMASKMOVP (#2342)ye-yeshun2025-02-121-67/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * fix: 0x2C: 'VMASKMOVPS Gx, Vx, Ex' Log: VMASKMOVPS读取内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: I197fc356edcac202b5a329c50c334d0166532e93 * fix: 0x2D: 'VMASKMOVPD Gx, Vx, Ex' Log: VMASKMOVPD读取内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: Ie11d93971aa92b141540a37bfdae0b3b060e3aea * fix: 0x2E: 'VMASKMOVPS Ex, Gx, Vx' Log: VMASKMOVPS写入内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: Ide5cb36dc03fc56480fdd45e7d96daed8557d849 * fix: 0x2F: 'VMASKMOVPD Ex, Gx, Vx' Log: VMASKMOVPD写入内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: I037de8568e9d2d29597fdf08f991d54e3cb2f6d9 * fix: 0x8E: 'VPMASKMOVD/Q Ex, Vx, Gx' Log: VPMASKMOVD/Q写入内存时, 如果某些mask位是0则不进行读写避免访问越界 Signed-off-by: YeshunYe <yeyeshun@uniontech.com> Change-Id: I0dc98a29ed933d953e137e777bc296149d94b10b * tests: add test for VPMASKMOV and VMASKMOVP Log: Signed-off-by: YeshunYe <yeyeshun@uniontech.com> --------- Signed-off-by: YeshunYe <yeyeshun@uniontech.com>
* [RCFILE] Improved support for windows setupptitSeb2025-02-121-1/+1
|
* [ARM64_DYNAREC] Fixed F0 0F B1 ocpode (emit_cmp32 can only be used once per ↵ptitSeb2025-02-111-10/+13
| | | | opcode, because of the df flags handling)
* [ARM64_DYNAREC] Fixed wrong COUNT operand in VPSLL{W,D,Q} (#2344)wannacu2025-02-111-12/+15
|
* [LA64_DYNAREC] Added F3 0F 52 RSQRTSS opcode (#2343)Yang Liu2025-02-111-0/+13
|
* [ARM64_DYNAREC] Added code on safeflags=2 to check if SI/DI memory overlap ↵ptitSeb2025-02-112-1/+15
| | | | on fast rep movsb opcode
* [LA64_DYNAREC] Added F2 0F 7D HSUBPS opcode (#2341)Yang Liu2025-02-111-0/+11
|
* [ARM64_DYNAREC] Some changes on shift opcode and OF handling, and added some ↵ptitSeb2025-02-101-31/+45
| | | | new profiles
* [ARM64_DYNAREC] Mostly cosmetic change on (I)DIV 8bits opcodeptitSeb2025-02-101-35/+31
|
* [LA64_DYNAREC] Added preliminary optimization for REP MOVSB (#2340)Yang Liu2025-02-102-0/+28
|
* [LA64_DYNAREC] Added more opcodes (#2339)Yang Liu2025-02-105-0/+201
|
* [DYNAREC] Fixed inst_size building that could be wrong when dynablock was ↵ptitSeb2025-02-099-14/+17
| | | | stopped for unknown opcode or other various reason
* [LA64_DYNREC] Added more opcodes (#2338)Yang Liu2025-02-095-0/+82
|
* [DYNAREC] Fixed diff logging prefix of pass2&3 (#2337)Yang Liu2025-02-091-4/+4
|
* [LA64_DYNAREC] Fixed newly added 66 0F BA /4 BT opcode (#2336)Yang Liu2025-02-091-1/+5
|
* [ARM64_DYNAREC] Fixed a potential segfault when signal happens while running ↵ptitSeb2025-02-091-0/+2
| | | | Interpreter
* [LA64_DYNAREC] Added more opcodes (#2333)Yang Liu2025-02-081-0/+11
|
* [ARM64_DYNAREC] Minor simplifications with the usage of GETEX (#2332)Yang Liu2025-02-081-14/+2
|
* [RV64_DYNAREC] Minor fixes and improvements on various opcodes (#2331)Yang Liu2025-02-082-29/+36
|
* [LA64_DYNAREC] Added more opcodes (#2330)Yang Liu2025-02-085-0/+178
|
* [LA64_DYNAREC] Added more opcodes (#2328)Yang Liu2025-02-083-0/+35
|
* [RV64_DYNAREC] Added aligned optim case for REP MOVSB (#2327)Yang Liu2025-02-084-1/+39
| | | | | * [RV64_DYNAREC] Added aligned optim case for REP MOVSB * fixed a typo
* [ARM64_DYNAREC] Optimized unaligned path for REP MOVSBptitSeb2025-02-081-1/+15
|
* [ARM64_DYNAREC] Added more aligned optim cases for REP MOVSB (#2326)Yang Liu2025-02-084-1/+18
|
* [RCFILE] Fixed ROLLING_LOG when setup in a profile onlyptitSeb2025-02-072-6/+13
|
* [LA64_DYNAREC] Added more opcodes (#2324)Yang Liu2025-02-072-0/+13
|
* [LA64_DYNAREC] Added more opcodes (#2323)Yang Liu2025-02-073-0/+30
|
* [LA64_DYNAREC] Added more 66 0F 38 opcodes (#2322)Yang Liu2025-02-071-0/+19
|
* [LA64_DYNAREC] Fixed F3 0F MOVSLDUP opcode (#2321)Yang Liu2025-02-071-1/+1
|