From 1ac4cdeae9b6dafdb533087ea6ad8fd63228a72e Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Wed, 9 Jul 2025 10:57:47 +0200 Subject: [ARM64_DYNAREC] Better handling of shift 0 for rcl/rct 16bits --- src/dynarec/arm64/dynarec_arm64_66.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/dynarec/arm64/dynarec_arm64_66.c b/src/dynarec/arm64/dynarec_arm64_66.c index 4c38482c..edbda902 100644 --- a/src/dynarec/arm64/dynarec_arm64_66.c +++ b/src/dynarec/arm64/dynarec_arm64_66.c @@ -1299,6 +1299,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } SETFLAGS(X_OF|X_CF, SF_SET_DF); ANDw_mask(x2, xRCX, 0, 0b00100); + CBZw_NEXT(x2); GETEW(x1, 0); CALL_(const_rcl16, x1, x3); EWBACK; @@ -1313,6 +1314,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } SETFLAGS(X_OF|X_CF, SF_SET_DF); ANDw_mask(x2, xRCX, 0, 0b00100); + CBZw_NEXT(x2); GETEW(x1, 0); CALL_(const_rcr16, x1, x3); EWBACK; -- cgit 1.4.1