From 2fb4dccff02becaeb83dd58d51da9053ec3fe256 Mon Sep 17 00:00:00 2001
From: xctan <xctan@cirno.icu>
Date: Tue, 2 May 2023 21:00:31 +0800
Subject: [RV64_DYNAREC] Added more opcodes (#751)

* [RV64_DYNAREC] Fixed 66F0 opcodes

* [RV64] Added space between extensions and RISC-V

* [RV64_DYNAREC] Added 66 0F E6 CVTTPD2DQ opcode

* [RV64_DYNAREC] Added 0F 0D /1 PREFETCHW opcode

* [RV64_DYNAREC] Added F3 0F 2D CVTSS2SI opcode

* [RV64_DYNAREC] Fixed 66 0F E6 CVTTPD2DQ opcode

* [RV64_DYNAREC] Added D1 /3 RCR opcode
---
 src/dynarec/rv64/dynarec_rv64_00_3.c   | 10 ++++++++++
 src/dynarec/rv64/dynarec_rv64_0f.c     | 12 ++++++++++++
 src/dynarec/rv64/dynarec_rv64_660f.c   | 33 +++++++++++++++++++++++++++++++++
 src/dynarec/rv64/dynarec_rv64_66f0.c   |  2 ++
 src/dynarec/rv64/dynarec_rv64_f30f.c   | 25 +++++++++++++++++++++++++
 src/dynarec/rv64/dynarec_rv64_helper.h | 11 +++++++++++
 src/main.c                             |  2 +-
 7 files changed, 94 insertions(+), 1 deletion(-)

diff --git a/src/dynarec/rv64/dynarec_rv64_00_3.c b/src/dynarec/rv64/dynarec_rv64_00_3.c
index 19d6815e..90332b60 100644
--- a/src/dynarec/rv64/dynarec_rv64_00_3.c
+++ b/src/dynarec/rv64/dynarec_rv64_00_3.c
@@ -432,6 +432,16 @@ uintptr_t dynarec64_00_3(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
                     WBACK;
                     if(!wback && !rex.w) ZEROUP(ed);
                     break;
+                case 3:
+                    INST_NAME("RCR Ed, 1");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_OF|X_CF, SF_SET);
+                    MOV32w(x2, 1);
+                    GETEDW(x4, x1, 0);
+                    CALL_(rex.w?((void*)rcr64):((void*)rcr32), ed, x4);
+                    WBACK;
+                    break;
                 case 4:
                 case 6:
                     INST_NAME("SHL Ed, 1");
diff --git a/src/dynarec/rv64/dynarec_rv64_0f.c b/src/dynarec/rv64/dynarec_rv64_0f.c
index e5e44a12..e6ac82d8 100644
--- a/src/dynarec/rv64/dynarec_rv64_0f.c
+++ b/src/dynarec/rv64/dynarec_rv64_0f.c
@@ -113,6 +113,18 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
             *ok = 0;
             break;
 
+        case 0x0D:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 1:
+                    INST_NAME("PREFETCHW");
+                    // nop without Zicbom, Zicbop, Zicboz extensions
+                    FAKEED;
+                    break;
+                default:    //???
+                    DEFAULT;
+            }
+            break;
 
         case 0x10:
             INST_NAME("MOVUPS Gx,Ex");
diff --git a/src/dynarec/rv64/dynarec_rv64_660f.c b/src/dynarec/rv64/dynarec_rv64_660f.c
index ed0ab0f8..6e19ab14 100644
--- a/src/dynarec/rv64/dynarec_rv64_660f.c
+++ b/src/dynarec/rv64/dynarec_rv64_660f.c
@@ -1703,6 +1703,39 @@ uintptr_t dynarec64_660F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
                 SH(x3, gback, 2*i);
             }
             break;
+        case 0xE6:
+            INST_NAME("CVTTPD2DQ Gx, Ex");
+            nextop = F8;
+            GETGX(x1);
+            GETEX(x2, 0);
+            v0 = fpu_get_scratch(dyn);
+            v1 = fpu_get_scratch(dyn);
+            FLD(v0, wback, 0);
+            FLD(v1, wback, 8);
+            if(!box64_dynarec_fastround) {
+                FSFLAGSI(xZR);  // // reset all bits
+            }
+            FCVTWD(x3, v0, RD_RTZ);
+            if(!box64_dynarec_fastround) {
+                FRFLAGS(x5);   // get back FPSR to check the IOC bit
+                ANDI(x5, x5, (1<<FR_NV)|(1<<FR_OF));
+                BEQ_MARK(x5, xZR);
+                MOV32w(x3, 0x80000000);
+                MARK;
+                FSFLAGSI(xZR);  // // reset all bits
+            }
+            FCVTWD(x4, v1, RD_RTZ);
+            if(!box64_dynarec_fastround) {
+                FRFLAGS(x5);   // get back FPSR to check the IOC bit
+                ANDI(x5, x5, (1<<FR_NV)|(1<<FR_OF));
+                BEQ_MARK2(x5, xZR);
+                MOV32w(x4, 0x80000000);
+                MARK2;
+            }
+            SW(x3, gback, 0);
+            SW(x4, gback, 4);
+            SD(xZR, gback, 8);
+            break;
         case 0xE7:
             INST_NAME("MOVNTDQ Ex, Gx");
             nextop = F8;
diff --git a/src/dynarec/rv64/dynarec_rv64_66f0.c b/src/dynarec/rv64/dynarec_rv64_66f0.c
index b1df0489..c0785742 100644
--- a/src/dynarec/rv64/dynarec_rv64_66f0.c
+++ b/src/dynarec/rv64/dynarec_rv64_66f0.c
@@ -130,4 +130,6 @@ uintptr_t dynarec64_66F0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
         default:
             DEFAULT;
     }
+
+    return addr;
 }
\ No newline at end of file
diff --git a/src/dynarec/rv64/dynarec_rv64_f30f.c b/src/dynarec/rv64/dynarec_rv64_f30f.c
index 77b8bf2d..ab7855da 100644
--- a/src/dynarec/rv64/dynarec_rv64_f30f.c
+++ b/src/dynarec/rv64/dynarec_rv64_f30f.c
@@ -121,6 +121,31 @@ uintptr_t dynarec64_F30F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
                 }
             }
             break;
+        case 0x2D:
+            INST_NAME("CVTSS2SI Gd, Ex");
+            nextop = F8;
+            GETGD;
+            GETEXSS(d0, 0);
+            if(!box64_dynarec_fastround) {
+                FSFLAGSI(xZR);  // // reset all bits
+            }
+            u8 = sse_setround(dyn, ninst, x5, x6);
+            FCVTSxw(gd, d0, RD_DYN);
+            x87_restoreround(dyn, ninst, u8);
+            if(!rex.w)
+                ZEROUP(gd);
+            if(!box64_dynarec_fastround) {
+                FRFLAGS(x5);   // get back FPSR to check the IOC bit
+                ANDI(x5, x5, (1<<FR_NV)|(1<<FR_OF));
+                CBZ_NEXT(x5);
+                if(rex.w) {
+                    MOV64x(gd, 0x8000000000000000LL);
+                } else {
+                    MOV32w(gd, 0x80000000);
+                }
+            }
+            break;
+
         case 0x51:
             INST_NAME("SQRTSS Gx, Ex");
             nextop = F8;
diff --git a/src/dynarec/rv64/dynarec_rv64_helper.h b/src/dynarec/rv64/dynarec_rv64_helper.h
index f6be2c94..b59dbfe7 100644
--- a/src/dynarec/rv64/dynarec_rv64_helper.h
+++ b/src/dynarec/rv64/dynarec_rv64_helper.h
@@ -109,6 +109,17 @@
                     LDxw(hint, wback, fixedaddress);    \
                     ed = hint;                          \
                 }
+//GETEDW can use hint for wback and ret for ed. wback is 0 if ed is xEAX..xEDI
+#define GETEDW(hint, ret, D)   if(MODREG) {             \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    MV(ret, ed);                        \
+                    wback = 0;                          \
+                } else {                                \
+                    SMREAD();                           \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, (hint==x2)?x1:x2, (hint==x1)?x1:x3, &fixedaddress, rex, NULL, 0, D); \
+                    ed = ret;                           \
+                    LDxw(ed, wback, fixedaddress);      \
+                }
 // GETGW extract x64 register in gd, that is i
 #define GETGW(i) gd = xRAX+((nextop&0x38)>>3)+(rex.r<<3); SLLI(i, gd, 48); SRLI(i, i, 48); gd = i;
 //GETEWW will use i for ed, and can use w for wback.
diff --git a/src/main.c b/src/main.c
index 31884fcc..27bfa9c0 100755
--- a/src/main.c
+++ b/src/main.c
@@ -362,7 +362,7 @@ HWCAP2_ECV
 #elif defined(RV64)
     void RV64_Detect_Function();
     RV64_Detect_Function();
-    printf_log(LOG_INFO, "Dynarec for RISC-V");
+    printf_log(LOG_INFO, "Dynarec for RISC-V ");
     printf_log(LOG_INFO, "With extension: I M A F D C");
     if(rv64_zba) printf_log(LOG_INFO, " Zba");
     if(rv64_zbb) printf_log(LOG_INFO, " Zbb");
-- 
cgit 1.4.1