From 4fadb26cf6e98e637a5f02cbb2e816faee097a29 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Sat, 13 May 2023 07:46:29 +0000
Subject: [RV64_DYNAREC] Added x9 as a new scratch register

---
 src/dynarec/rv64/rv64_emitter.h |  1 +
 src/dynarec/rv64/rv64_epilog.S  | 43 +++++++++++++++++++++--------------------
 src/dynarec/rv64/rv64_prolog.S  | 43 +++++++++++++++++++++--------------------
 3 files changed, 45 insertions(+), 42 deletions(-)

diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h
index bf834507..3ee6bd11 100644
--- a/src/dynarec/rv64/rv64_emitter.h
+++ b/src/dynarec/rv64/rv64_emitter.h
@@ -74,6 +74,7 @@ f28–31  ft8–11  FP temporaries                  Caller
 #define x4      14
 #define x5      15
 #define x6      6
+#define x9      9
 // used to clear the upper 32bits
 #define xMASK   5
 // 32bits version of scratch
diff --git a/src/dynarec/rv64/rv64_epilog.S b/src/dynarec/rv64/rv64_epilog.S
index 6a299d9d..17dc117f 100644
--- a/src/dynarec/rv64/rv64_epilog.S
+++ b/src/dynarec/rv64/rv64_epilog.S
@@ -39,26 +39,27 @@ rv64_epilog:
 rv64_epilog_fast:
     ld      ra, (sp)  // save ra
     ld      x8, 8(sp) // save fp
-    ld      x18, 16(sp)
-    ld      x19, 24(sp)
-    ld      x20, 32(sp)
-    ld      x21, 40(sp)
-    ld      x22, 48(sp)
-    ld      x23, 56(sp)
-    ld      x24, 64(sp)
-    ld      x25, 72(sp)
-    ld      x26, 80(sp)
-    ld      x27, 88(sp)
-    fld     f18, (12*8)(sp)
-    fld     f19, (13*8)(sp)
-    fld     f20, (14*8)(sp)
-    fld     f21, (15*8)(sp)
-    fld     f22, (16*8)(sp)
-    fld     f23, (17*8)(sp)
-    fld     f24, (18*8)(sp)
-    fld     f25, (19*8)(sp)
-    fld     f26, (20*8)(sp)
-    fld     f27, (21*8)(sp)
-    addi    sp,  sp, (8 * 22)
+    ld      x18, (2*8)(sp)
+    ld      x19, (3*8)(sp)
+    ld      x20, (4*8)(sp)
+    ld      x21, (5*8)(sp)
+    ld      x22, (6*8)(sp)
+    ld      x23, (7*8)(sp)
+    ld      x24, (8*8)(sp)
+    ld      x25, (9*8)(sp)
+    ld      x26, (10*8)(sp)
+    ld      x27, (11*8)(sp)
+    ld      x9,  (12*8)(sp)
+    fld     f18, (13*8)(sp)
+    fld     f19, (14*8)(sp)
+    fld     f20, (15*8)(sp)
+    fld     f21, (16*8)(sp)
+    fld     f22, (17*8)(sp)
+    fld     f23, (19*8)(sp)
+    fld     f24, (19*8)(sp)
+    fld     f25, (20*8)(sp)
+    fld     f26, (21*8)(sp)
+    fld     f27, (22*8)(sp)
+    addi    sp,  sp, (8 * 24)
     //end, return...
     ret
diff --git a/src/dynarec/rv64/rv64_prolog.S b/src/dynarec/rv64/rv64_prolog.S
index 0817bdc1..96a85d3b 100644
--- a/src/dynarec/rv64/rv64_prolog.S
+++ b/src/dynarec/rv64/rv64_prolog.S
@@ -11,29 +11,30 @@
 .global rv64_prolog
 rv64_prolog:
     //save all 18 used register
-    addi    sp,  sp, -(8 * 22)
+    addi    sp,  sp, -(8 * 24)  // 16 bytes aligned
     sd      ra, (sp)  // save ra
     sd      x8, 8(sp) // save fp
-    sd      x18, 16(sp)
-    sd      x19, 24(sp)
-    sd      x20, 32(sp)
-    sd      x21, 40(sp)
-    sd      x22, 48(sp)
-    sd      x23, 56(sp)
-    sd      x24, 64(sp)
-    sd      x25, 72(sp)
-    sd      x26, 80(sp)
-    sd      x27, 88(sp)
-    fsd     f18, (12*8)(sp)
-    fsd     f19, (13*8)(sp)
-    fsd     f20, (14*8)(sp)
-    fsd     f21, (15*8)(sp)
-    fsd     f22, (16*8)(sp)
-    fsd     f23, (17*8)(sp)
-    fsd     f24, (18*8)(sp)
-    fsd     f25, (19*8)(sp)
-    fsd     f26, (20*8)(sp)
-    fsd     f27, (21*8)(sp)
+    sd      x18, (2*8)(sp)
+    sd      x19, (3*8)(sp)
+    sd      x20, (4*8)(sp)
+    sd      x21, (5*8)(sp)
+    sd      x22, (6*8)(sp)
+    sd      x23, (7*8)(sp)
+    sd      x24, (8*8)(sp)
+    sd      x25, (9*8)(sp)
+    sd      x26, (10*8)(sp)
+    sd      x27, (11*8)(sp)
+    sd      x9,  (12*8)(sp)
+    fsd     f18, (13*8)(sp)
+    fsd     f19, (14*8)(sp)
+    fsd     f20, (15*8)(sp)
+    fsd     f21, (16*8)(sp)
+    fsd     f22, (17*8)(sp)
+    fsd     f23, (19*8)(sp)
+    fsd     f24, (19*8)(sp)
+    fsd     f25, (20*8)(sp)
+    fsd     f26, (21*8)(sp)
+    fsd     f27, (22*8)(sp)
     //setup emu -> register
     ld      x16, (a0)
     ld      x17, 8(a0)
-- 
cgit 1.4.1