From 60396f58c0aaa4d5deca5663ecd91077a10048cf Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Tue, 11 Feb 2025 22:52:52 +0100 Subject: [ARM64_DYNAREC] Fixed F0 0F B1 ocpode (emit_cmp32 can only be used once per opcode, because of the df flags handling) --- src/dynarec/arm64/dynarec_arm64_f0.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/src/dynarec/arm64/dynarec_arm64_f0.c b/src/dynarec/arm64/dynarec_arm64_f0.c index e0e74535..19ecc0a4 100644 --- a/src/dynarec/arm64/dynarec_arm64_f0.c +++ b/src/dynarec/arm64/dynarec_arm64_f0.c @@ -354,15 +354,17 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin if(arm64_atomics) { UFLAG_IF { MOVxw_REG(x1, xRAX); - CASALxw(xRAX, gd, wback); + CASALxw(x1, gd, wback); SMDMB(); - emit_cmp32(dyn, ninst, rex, x1, xRAX, x3, x4, x5); + if(!ALIGNED_ATOMICxw) { + B_MARK_nocond; + } } else { CASALxw(xRAX, gd, wback); SMDMB(); - } - if(!ALIGNED_ATOMICxw) { - B_NEXT_nocond; + if(!ALIGNED_ATOMICxw) { + B_NEXT_nocond; + } } } else { MARKLOCK; @@ -391,11 +393,12 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin STRxw_U12(gd, wback, 0); SMDMB(); } - if(!ALIGNED_ATOMICxw || !arm64_atomics) { - MARK; - // Common part (and fallback for EAX != Ed) - UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, x1, x3, x4, x5);} - MOVxw_REG(xRAX, x1); // upper par of RAX will be erase on 32bits, no mater what + MARK; + // Common part (and fallback for EAX != Ed) + UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, x1, x3, x4, x5); MOVxw_REG(xRAX, x1);} + else { + if(!ALIGNED_ATOMICxw || !arm64_atomics) + MOVxw_REG(xRAX, x1); // upper par of RAX will be erase on 32bits, no mater what } } break; -- cgit 1.4.1