From 67b2151e3ca30fd33aa770b5d5c0ba2b3ecf2fc0 Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Fri, 11 Oct 2024 02:58:45 +0800 Subject: [RV64_DYNAREC] Added more opcode for vector and some fixes too (#1920) --- src/dynarec/rv64/dynarec_rv64_660f_vector.c | 2 +- src/dynarec/rv64/dynarec_rv64_f20f_vector.c | 41 +++++++++++++++++++++++++++++ src/dynarec/rv64/dynarec_rv64_f30f.c | 2 +- src/dynarec/rv64/dynarec_rv64_f30f_vector.c | 34 ++++++++++-------------- 4 files changed, 57 insertions(+), 22 deletions(-) diff --git a/src/dynarec/rv64/dynarec_rv64_660f_vector.c b/src/dynarec/rv64/dynarec_rv64_660f_vector.c index ff62c3c4..e610abea 100644 --- a/src/dynarec/rv64/dynarec_rv64_660f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_660f_vector.c @@ -1089,8 +1089,8 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i case 0x6E: INST_NAME("MOVD Gx, Ed"); nextop = F8; - GETED(0); GETGX_empty_vector(v0); + GETED(0); if (rex.w) { SET_ELEMENT_WIDTH(x3, VECTOR_SEW64, 1); } else { diff --git a/src/dynarec/rv64/dynarec_rv64_f20f_vector.c b/src/dynarec/rv64/dynarec_rv64_f20f_vector.c index 1805b06d..ed53b0f7 100644 --- a/src/dynarec/rv64/dynarec_rv64_f20f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_f20f_vector.c @@ -97,8 +97,49 @@ uintptr_t dynarec64_F20F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i SMWRITE2(); } break; + case 0x2A: + INST_NAME("CVTSI2SD Gx, Ed"); + nextop = F8; + if (rex.w) { + SET_ELEMENT_WIDTH(x3, VECTOR_SEW64, 1); + GETGX_vector(v0, 1, VECTOR_SEW64); + GETED(0); + FCVTDL(v0, ed, RD_RNE); + } else { + SET_ELEMENT_WIDTH(x3, VECTOR_SEW32, 1); + GETGX_vector(v0, 1, VECTOR_SEW32); + GETED(0); + FCVTDW(v0, ed, RD_RNE); + SET_ELEMENT_WIDTH(x3, VECTOR_SEW64, 1); + } + if (rv64_xtheadvector) { + v1 = fpu_get_scratch(dyn); + VFMV_S_F(v1, v0); + vector_loadmask(dyn, ninst, VMASK, 0b01, x4, 1); + VMERGE_VVM(v0, v0, v1); // implies VMASK + } else { + VFMV_S_F(v0, v0); + } + break; case 0x38: return 0; + case 0x59: + INST_NAME("MULSD Gx, Ex"); // TODO: box64_dynarec_fastnan + nextop = F8; + SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + GETGX_vector(v0, 1, VECTOR_SEW64); + v1 = fpu_get_scratch(dyn); + vector_loadmask(dyn, ninst, VMASK, 0b01, x4, 1); + if (MODREG) { + v1 = sse_get_reg_vector(dyn, ninst, x1, (nextop & 7) + (rex.b << 3), 0, VECTOR_SEW64); + } else { + SMREAD(); + v1 = fpu_get_scratch(dyn); + addr = geted(dyn, addr, ninst, nextop, &ed, x1, x2, &fixedaddress, rex, NULL, 0, 0); + VLE64_V(v1, ed, VECTOR_MASKED, VECTOR_NFIELD1); + } + VFMUL_VV(v0, v0, v1, VECTOR_MASKED); + break; default: DEFAULT_VECTOR; } return addr; diff --git a/src/dynarec/rv64/dynarec_rv64_f30f.c b/src/dynarec/rv64/dynarec_rv64_f30f.c index a4f19358..75f4c92f 100644 --- a/src/dynarec/rv64/dynarec_rv64_f30f.c +++ b/src/dynarec/rv64/dynarec_rv64_f30f.c @@ -212,7 +212,7 @@ uintptr_t dynarec64_F30F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int FADDS(v0, v0, d0); break; case 0x59: - INST_NAME("MULSS Gx, Ex"); + INST_NAME("MULSS Gx, Ex"); // TODO: box64_dynarec_fastnan nextop = F8; GETGXSS(v0); GETEXSS(d0, 0); diff --git a/src/dynarec/rv64/dynarec_rv64_f30f_vector.c b/src/dynarec/rv64/dynarec_rv64_f30f_vector.c index 95dacbbe..8146bcab 100644 --- a/src/dynarec/rv64/dynarec_rv64_f30f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_f30f_vector.c @@ -104,37 +104,31 @@ uintptr_t dynarec64_F30F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i case 0x2A: INST_NAME("CVTSI2SS Gx, Ed"); nextop = F8; - GETED(0); if (rex.w) { - SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1); + SET_ELEMENT_WIDTH(x3, VECTOR_SEW64, 1); GETGX_vector(v0, 1, VECTOR_SEW64); + GETED(0); FCVTSL(v0, ed, RD_RNE); - if (rv64_xtheadvector) { - v1 = fpu_get_scratch(dyn); - VFMV_S_F(v1, v0); - vector_loadmask(dyn, ninst, VMASK, 0b01, x4, 1); - VMERGE_VVM(v0, v0, v1); // implies VMASK - } else { - VFMV_S_F(v0, v0); - } + SET_ELEMENT_WIDTH(x3, VECTOR_SEW32, 1); } else { - SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1); + SET_ELEMENT_WIDTH(x3, VECTOR_SEW32, 1); GETGX_vector(v0, 1, VECTOR_SEW32); + GETED(0); FCVTSW(v0, ed, RD_RNE); - if (rv64_xtheadvector) { - v1 = fpu_get_scratch(dyn); - VFMV_S_F(v1, v0); - vector_loadmask(dyn, ninst, VMASK, 0b0001, x4, 1); - VMERGE_VVM(v0, v0, v1); // implies VMASK - } else { - VFMV_S_F(v0, v0); - } + } + if (rv64_xtheadvector) { + v1 = fpu_get_scratch(dyn); + VFMV_S_F(v1, v0); + vector_loadmask(dyn, ninst, VMASK, 0b0001, x4, 1); + VMERGE_VVM(v0, v0, v1); // implies VMASK + } else { + VFMV_S_F(v0, v0); } break; case 0x38: return 0; case 0x59: - INST_NAME("MULSS Gx, Ex"); + INST_NAME("MULSS Gx, Ex"); // TODO: box64_dynarec_fastnan nextop = F8; SET_ELEMENT_WIDTH(x1, VECTOR_SEW32, 1); GETGX_vector(v0, 1, VECTOR_SEW32); -- cgit 1.4.1