From 978cd2ec51fe74e0e64a0caa565d36ef6b85bb08 Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Tue, 14 Mar 2023 15:36:07 +0800 Subject: [RV64_DYNAREC] Small optimization for 31 XOR opcode (#561) --- src/dynarec/rv64/dynarec_rv64_emit_logic.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/dynarec/rv64/dynarec_rv64_emit_logic.c b/src/dynarec/rv64/dynarec_rv64_emit_logic.c index e9086276..b36867f8 100644 --- a/src/dynarec/rv64/dynarec_rv64_emit_logic.c +++ b/src/dynarec/rv64/dynarec_rv64_emit_logic.c @@ -33,7 +33,17 @@ void emit_xor32(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s SET_DFNONE(s4); } - XORxw(s1, s1, s2); + XOR(s1, s1, s2); + + // test sign bit before zeroup. + IFX(X_SF) { + BGE(s1, xZR, 4); + ORI(xFlags, xFlags, 1 << F_SF); + } + if (!rex.w) { + ZEROUP(s1); + } + IFX(X_PEND) { SDxw(s1, xEmu, offsetof(x64emu_t, res)); } @@ -42,11 +52,6 @@ void emit_xor32(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, int s2, int s BNEZ(s1, 4); ORI(xFlags, xFlags, F_ZF); } - IFX(X_SF) { - SRLI(s3, s1, rex.w?63:31); - BEQZ(s3, 4); - ORI(xFlags, xFlags, 1 << F_SF); - } IFX(X_PF) { emit_pf(dyn, ninst, s1, s3, s4); } -- cgit 1.4.1