From a3dcaf42847ef2fb67904474e02a05445e3b8a39 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Wed, 24 Mar 2021 14:49:31 +0100 Subject: [DYNAREC] Added F2 0F 5D/5F opcodes --- src/dynarec/dynarec_arm64_f20f.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/dynarec/dynarec_arm64_f20f.c b/src/dynarec/dynarec_arm64_f20f.c index 7c0fb038..c153f907 100755 --- a/src/dynarec/dynarec_arm64_f20f.c +++ b/src/dynarec/dynarec_arm64_f20f.c @@ -156,7 +156,17 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n FSUBD(d1, v0, d0); VMOVeD(v0, 0, d1, 0); break; - + case 0x5D: + INST_NAME("MINSD Gx, Ex"); + nextop = F8; + gd = (nextop&0x38)>>3; + v0 = sse_get_reg(dyn, ninst, x1, gd); + GETEX(v1, 0); + // MINSD: if any input is NaN, or Ex[0] Gx[0] + d0 = fpu_get_scratch(dyn); + FMINNMD(d0, v0, v1); // NaN handling may be slightly different, is that a problem? + VMOVeD(v0, 0, d0, 0); // to not erase uper part + break; case 0x5E: INST_NAME("DIVSD Gx, Ex"); nextop = F8; @@ -166,6 +176,17 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n FDIVD(d1, v0, d0); VMOVeD(v0, 0, d1, 0); break; + case 0x5F: + INST_NAME("MAXSD Gx, Ex"); + nextop = F8; + gd = (nextop&0x38)>>3; + v0 = sse_get_reg(dyn, ninst, x1, gd); + GETEX(v1, 0); + // MAXSD: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0] + d0 = fpu_get_scratch(dyn); + FMAXNMD(d0, v0, v1); // NaN handling may be slightly different, is that a problem? + VMOVeD(v0, 0, d0, 0); // to not erase uper part + break; case 0x7C: INST_NAME("HADDPS Gx, Ex"); -- cgit 1.4.1