From a6737720f4abca8794fffbff1ba0dfbd9ef9b22b Mon Sep 17 00:00:00 2001
From: xctan <xctan@cirno.icu>
Date: Thu, 1 Jun 2023 23:44:18 +0800
Subject: [RV64_DYNAREC] Added F0 80 /1 LOCK OR opcode for ICEY (#815)

---
 src/dynarec/rv64/dynarec_rv64_f0.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/src/dynarec/rv64/dynarec_rv64_f0.c b/src/dynarec/rv64/dynarec_rv64_f0.c
index 6bb11fbd..513bb3d8 100644
--- a/src/dynarec/rv64/dynarec_rv64_f0.c
+++ b/src/dynarec/rv64/dynarec_rv64_f0.c
@@ -386,6 +386,43 @@ uintptr_t dynarec64_F0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
             }
             SMDMB();
             break;
+        case 0x80:
+            nextop = F8;
+            SMDMB();
+            switch((nextop>>3)&7) {
+                case 1: // OR
+                    INST_NAME("LOCK OR Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_or8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        EBBACK(x5, 0);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, x1, &fixedaddress, rex, LOCK_LOCK, 0, 1);
+                        u8 = F8;
+                        ANDI(x2, wback, 3);
+                        SLLI(x2, x2, 3);     // offset in bits
+                        ANDI(x3, wback, ~3); // aligned addr
+                        ADDI(x1, xZR, u8);
+                        SLL(x1, x1, x2);     // Ib << offset
+                        MARKLOCK;
+                        LR_W(x4, x3, 1, 1);
+                        OR(x6, x4, x1);
+                        SC_W(x6, x6, x3, 1, 1);
+                        BNEZ_MARKLOCK(x6);
+                        IFX(X_ALL|X_PEND) {
+                            SRL(x1, x4, x2);
+                            ANDI(x1, x1, 0xFF);
+                            emit_or8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        }
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            SMDMB();
+            break;
         case 0x81:
         case 0x83:
             nextop = F8;
-- 
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