From dce81673afefcd07f04b5d3e581c2cdf339903fd Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Mon, 11 Aug 2025 21:32:13 +0800 Subject: [RV64_DYNAREC] Fixed F0 10 LOCK ADC opcode (#2927) --- src/dynarec/rv64/dynarec_rv64_f0.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/dynarec/rv64/dynarec_rv64_f0.c b/src/dynarec/rv64/dynarec_rv64_f0.c index 4a7f3257..d4197612 100644 --- a/src/dynarec/rv64/dynarec_rv64_f0.c +++ b/src/dynarec/rv64/dynarec_rv64_f0.c @@ -486,9 +486,9 @@ uintptr_t dynarec64_F0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni B_MARK3_nocond; MARK; SLLI(x3, x3, 3); - MOV_U12(x4, 0xff); + ADDI(x4, xZR, 0xff); ANDI(wback, wback, ~3); // aligning address - SLLI(x4, x4, x3); // x4 = byte mask + SLL(x4, x4, x3); // x4 = byte mask NOT(x5, x4); // x5 = ~mask SLL(x2, x2, x3); // x2 = extented Gb MARK2; @@ -499,12 +499,15 @@ uintptr_t dynarec64_F0(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni ANDI(x4, xFlags, 1 << F_CF); SLL(x4, x4, x3); // extented ADDW(x5, x5, x4); // x5 = adc + ADDI(x4, xZR, 0xff); + SLL(x4, x4, x3); + AND(x5, x5, x4); OR(x5, x5, x6); SC_W(x4, x5, wback, 1, 1); BNEZ_MARK2(x4); IFXORNAT (X_ALL | X_PEND) { - SRLI(x2, x2, x3); // Gb - SRLI(x4, x7, x3); // Eb + SRL(x2, x2, x3); // Gb + SRL(x4, x7, x3); // Eb } MARK3; IFXORNAT (X_ALL | X_PEND) { -- cgit 1.4.1