From f810fa262d48108e107604ce38c78ee0ae4e8961 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sat, 1 Apr 2023 17:22:02 +0000 Subject: [RV64_DYNAREC] Some more fixes to float operations (fixes regression in WorldOfGoo) --- src/dynarec/rv64/dynarec_rv64_0f.c | 4 ++-- src/dynarec/rv64/dynarec_rv64_660f.c | 4 ++-- src/dynarec/rv64/dynarec_rv64_df.c | 1 + src/dynarec/rv64/dynarec_rv64_helper.c | 6 +++++- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/dynarec/rv64/dynarec_rv64_0f.c b/src/dynarec/rv64/dynarec_rv64_0f.c index d373bab1..f080581d 100644 --- a/src/dynarec/rv64/dynarec_rv64_0f.c +++ b/src/dynarec/rv64/dynarec_rv64_0f.c @@ -220,6 +220,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni case 0x2F: if(opcode==0x2F) {INST_NAME("COMISS Gx, Ex");} else {INST_NAME("UCOMISS Gx, Ex");} SETFLAGS(X_ALL, SF_SET); + SET_DFNONE(); nextop = F8; GETGXSS(d0); GETEXSS(v0, 0); @@ -229,8 +230,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni FEQS(x3, d0, d0); FEQS(x2, v0, v0); AND(x2, x2, x3); - XORI(x2, x2, 1); - BEQ_MARK(x2, xZR); + BNE_MARK(x2, xZR); ORI(xFlags, xFlags, (1<e.ssecache[a].v!=-1) { + if(dyn->e.ssecache[a].single!=single && single) { + // need to wipe the half high 32bits of old Double because we now have a single + SW(xZR, xEmu, offsetof(x64emu_t, xmm[a])+4); + } dyn->e.ssecache[a].single = single; - dyn->e.extcache[dyn->e.ssecache[a].reg].t = single?EXT_CACHE_SS:EXT_CACHE_SD; + dyn->e.extcache[EXTIDX(dyn->e.ssecache[a].reg)].t = single?EXT_CACHE_SS:EXT_CACHE_SD; return dyn->e.ssecache[a].reg; } dyn->e.ssecache[a].reg = fpu_get_reg_xmm(dyn, single?EXT_CACHE_SS:EXT_CACHE_SD, a); -- cgit 1.4.1