From 12c40a5b804143cee0d538c4de4b526522bcfcd2 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Tue, 24 Oct 2023 16:59:40 +0200 Subject: [32BITS] Added 66 06/07 and 66 1E/1F opcodes ([ARM64_DYNAREC] too) --- src/dynarec/arm64/dynarec_arm64_66.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'src/dynarec') diff --git a/src/dynarec/arm64/dynarec_arm64_66.c b/src/dynarec/arm64/dynarec_arm64_66.c index b3504b48..c41c19ef 100644 --- a/src/dynarec/arm64/dynarec_arm64_66.c +++ b/src/dynarec/arm64/dynarec_arm64_66.c @@ -83,6 +83,25 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_add16(dyn, ninst, x1, x2, x3, x4); BFIx(xRAX, x1, 0, 16); break; + case 0x06: + if(rex.is32bits) { + INST_NAME("PUSH ES"); + LDRH_U12(x1, xEmu, offsetof(x64emu_t, segs[_ES])); + PUSH1_32(x1); + } else { + DEFAULT; + } + break; + case 0x07: + if(rex.is32bits) { + INST_NAME("POP ES"); + POP1_32(x1); + STRH_U12(x1, xEmu, offsetof(x64emu_t, segs[_ES])); + STRw_U12(xZR, xEmu, offsetof(x64emu_t, segs_serial[_ES])); + } else { + DEFAULT; + } + break; case 0x09: INST_NAME("OR Ew, Gw"); @@ -176,6 +195,25 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_sbb16(dyn, ninst, x1, x2, x3, x4); BFIx(xRAX, x1, 0, 16); break; + case 0x1E: + if(rex.is32bits) { + INST_NAME("PUSH DS"); + LDRH_U12(x1, xEmu, offsetof(x64emu_t, segs[_DS])); + PUSH1_32(x1); + } else { + DEFAULT; + } + break; + case 0x1F: + if(rex.is32bits) { + INST_NAME("POP DS"); + POP1_32(x1); + STRH_U12(x1, xEmu, offsetof(x64emu_t, segs[_DS])); + STRw_U12(xZR, xEmu, offsetof(x64emu_t, segs_serial[_DS])); + } else { + DEFAULT; + } + break; case 0x21: INST_NAME("AND Ew, Gw"); -- cgit 1.4.1