From 36e5fb50ecfe4a152782c42cf49ce9d14ffc46ea Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Mon, 19 Jul 2021 13:31:11 +0200 Subject: Added F3 0F BD opcode ([DYNAREC] too) (for #27) --- src/dynarec/dynarec_arm64_f30f.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/dynarec') diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c index b8479d5c..8c87b790 100755 --- a/src/dynarec/dynarec_arm64_f30f.c +++ b/src/dynarec/dynarec_arm64_f30f.c @@ -363,6 +363,20 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n CSETw(x1, cEQ); BFIw(xFlags, x1, F_ZF, 1); // ZF = is dest 0? break; + case 0xBD: + INST_NAME("LZCNT Gd, Ed"); + SETFLAGS(X_CF|X_ZF, SF_SUBSET); + SET_DFNONE(x1); + nextop = F8; + GETED(0); + GETGD; + TSTxw_REG(ed, ed); + BFIw(xFlags, x1, F_CF, 1); // CF = is source 0? + CLZxw(gd, x1); // x2 gets leading 0 == LZCNT + TSTxw_REG(gd, gd); + CSETw(x1, cEQ); + BFIw(xFlags, x1, F_ZF, 1); // ZF = is dest 0? + break; case 0xC2: INST_NAME("CMPSS Gx, Ex, Ib"); -- cgit 1.4.1