From bb0a445a6b57091fe5b878b09668d25edcb1e7ee Mon Sep 17 00:00:00 2001 From: olegos2 <74909582+olegos2@users.noreply.github.com> Date: Sat, 28 Dec 2024 21:06:51 +0500 Subject: Spelling/typo fixes in code and documentation updates (#2223) * Fix typo DLOpenned->DLOpened * Fix a typo in comments: versionned->versioned * Fix a typo in comment: cleanning->cleaning * Update COMPILE.md and USAGE.md * A few more typos in comments --- src/dynarec/arm64/dynarec_arm64_helper.c | 4 ++-- src/dynarec/dynarec_private.h | 2 +- src/dynarec/la64/dynarec_la64_helper.c | 4 ++-- src/dynarec/rv64/dynarec_rv64_helper.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/dynarec') diff --git a/src/dynarec/arm64/dynarec_arm64_helper.c b/src/dynarec/arm64/dynarec_arm64_helper.c index 3833644e..2a51678e 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.c +++ b/src/dynarec/arm64/dynarec_arm64_helper.c @@ -2217,7 +2217,7 @@ static void fpuCacheTransform(dynarec_arm_t* dyn, int ninst, int s1, int s2, int neoncache_t cache = dyn->n; int s1_val = 0; int s2_val = 0; - // unload every uneeded cache + // unload every unneeded cache // ymm0 first int s3_top = 1; uint16_t to_purge = dyn->ymm_zero&~dyn->insts[i2].ymm0_in; @@ -2233,7 +2233,7 @@ static void fpuCacheTransform(dynarec_arm_t* dyn, int ninst, int s1, int s2, int } } s3_top = 0xffff; - // check SSE first, than MMX, in order, to optimise successive memory write + // check SSE first, than MMX, in order, to optimize successive memory write for(int i=0; i<16; ++i) { int j=findCacheSlot(dyn, ninst, NEON_CACHE_XMMW, i, &cache); if(j>=0 && findCacheSlot(dyn, ninst, NEON_CACHE_XMMW, i, &cache_i2)==-1) diff --git a/src/dynarec/dynarec_private.h b/src/dynarec/dynarec_private.h index 20a22f7c..09ba152d 100644 --- a/src/dynarec/dynarec_private.h +++ b/src/dynarec/dynarec_private.h @@ -39,7 +39,7 @@ typedef struct instruction_x64_s { int jmp_insts; // instuction to jump to (-1 if out of the block) uint8_t jmp_cond:1; // 1 of conditionnal jump uint8_t has_next:1; // does this opcode can continue to the next? - uint8_t has_callret:1; // this instruction have an optimised call setup + uint8_t has_callret:1; // this instruction have an optimized call setup uint8_t alive:1; // this opcode gets executed (0 if dead code in that block) uint8_t barrier; // next instruction is a jump point, so no optim allowed uint8_t state_flags;// One of SF_XXX state diff --git a/src/dynarec/la64/dynarec_la64_helper.c b/src/dynarec/la64/dynarec_la64_helper.c index b6448035..3e622517 100644 --- a/src/dynarec/la64/dynarec_la64_helper.c +++ b/src/dynarec/la64/dynarec_la64_helper.c @@ -1256,8 +1256,8 @@ static void fpuCacheTransform(dynarec_la64_t* dyn, int ninst, int s1, int s2, in lsxcache_t cache = dyn->lsx; int s1_val = 0; int s2_val = 0; - // unload every uneeded cache - // check SSE first, than MMX, in order, for optimisation issue + // unload every unneeded cache + // check SSE first, than MMX, in order, for optimization issue for (int i = 0; i < 16; ++i) { int j = findCacheSlot(dyn, ninst, LSX_CACHE_XMMW, i, &cache); if (j >= 0 && findCacheSlot(dyn, ninst, LSX_CACHE_XMMW, i, &cache_i2) == -1) diff --git a/src/dynarec/rv64/dynarec_rv64_helper.c b/src/dynarec/rv64/dynarec_rv64_helper.c index 8aa14e53..3b73d8b4 100644 --- a/src/dynarec/rv64/dynarec_rv64_helper.c +++ b/src/dynarec/rv64/dynarec_rv64_helper.c @@ -2620,7 +2620,7 @@ static void fpuCacheTransform(dynarec_rv64_t* dyn, int ninst, int s1, int s2, in int s1_val = 0; int s2_val = 0; // unload every unneeded cache - // check SSE first, than MMX, in order, for optimisation issue + // check SSE first, than MMX, in order, for optimization issue for (int i = 0; i < 16; ++i) { int j = findCacheSlot(dyn, ninst, EXT_CACHE_SS, i, &cache); if (j >= 0 && findCacheSlot(dyn, ninst, EXT_CACHE_SS, i, &cache_i2) == -1) -- cgit 1.4.1