From d8ea2d637b63460cbe2c6cfd357202e333d5b70e Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Sat, 5 Mar 2022 21:25:30 +0100
Subject: Added 64 F3 0F 6F opcode ([DYNAREC] too) (for #241)

---
 src/dynarec/arm64/dynarec_arm64_64.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'src/dynarec')

diff --git a/src/dynarec/arm64/dynarec_arm64_64.c b/src/dynarec/arm64/dynarec_arm64_64.c
index 594bb7b5..da52b278 100644
--- a/src/dynarec/arm64/dynarec_arm64_64.c
+++ b/src/dynarec/arm64/dynarec_arm64_64.c
@@ -170,6 +170,29 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     }
                     break;
 
+                case 0x6F:
+                    switch(rep) {
+                        case 2:
+                            INST_NAME("MOVDQU Gx,Ex");// no alignment constraint on NEON here, so same as MOVDQA
+                            nextop = F8;
+                            GETG;
+                            v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                            if(MODREG) {
+                                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                                VMOVQ(v0, v1);
+                            } else {
+                                grab_segdata(dyn, addr, ninst, x4, seg);
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
+                                ADDx_REG(x4, x4, ed);
+                                VLDR128_U12(v0, ed, fixedaddress);
+                            }
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
+
+
                 case 0xAF:
                     INST_NAME("IMUL Gd, Ed");
                     SETFLAGS(X_ALL, SF_PENDING);
-- 
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