From 2fb4dccff02becaeb83dd58d51da9053ec3fe256 Mon Sep 17 00:00:00 2001 From: xctan Date: Tue, 2 May 2023 21:00:31 +0800 Subject: [RV64_DYNAREC] Added more opcodes (#751) * [RV64_DYNAREC] Fixed 66F0 opcodes * [RV64] Added space between extensions and RISC-V * [RV64_DYNAREC] Added 66 0F E6 CVTTPD2DQ opcode * [RV64_DYNAREC] Added 0F 0D /1 PREFETCHW opcode * [RV64_DYNAREC] Added F3 0F 2D CVTSS2SI opcode * [RV64_DYNAREC] Fixed 66 0F E6 CVTTPD2DQ opcode * [RV64_DYNAREC] Added D1 /3 RCR opcode --- src/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/main.c') diff --git a/src/main.c b/src/main.c index 31884fcc..27bfa9c0 100755 --- a/src/main.c +++ b/src/main.c @@ -362,7 +362,7 @@ HWCAP2_ECV #elif defined(RV64) void RV64_Detect_Function(); RV64_Detect_Function(); - printf_log(LOG_INFO, "Dynarec for RISC-V"); + printf_log(LOG_INFO, "Dynarec for RISC-V "); printf_log(LOG_INFO, "With extension: I M A F D C"); if(rv64_zba) printf_log(LOG_INFO, " Zba"); if(rv64_zbb) printf_log(LOG_INFO, " Zbb"); -- cgit 1.4.1