From 02c24dffdc4c802bf1c9dedd180092b17684eae3 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Fri, 7 Apr 2023 13:31:38 +0200 Subject: [ARM64_DYNAREC] Fixed, again, FASTROUND=0 for 66 0F E6 opcode --- src/dynarec/arm64/dynarec_arm64_660f.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c index c457e760..8461fbcf 100755 --- a/src/dynarec/arm64/dynarec_arm64_660f.c +++ b/src/dynarec/arm64/dynarec_arm64_660f.c @@ -2233,16 +2233,15 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n MSR_fpsr(x5); ORRw_mask(x4, xZR, 1, 0); //0x80000000 d0 = fpu_get_scratch(dyn); - for(int i=1; i>=0; --i) { + for(int i=0; i<2; ++i) { BFCw(x5, FPSR_IOC, 1); // reset IOC bit MSR_fpsr(x5); if(i) { VMOVeD(d0, 0, v1, i); - FRINTZD(d0, d0); + FCVTZSwD(x1, d0); } else { - FRINTZD(d0, v1); + FCVTZSwD(x1, v1); } - FCVTZSwD(x1, d0); MRS_fpsr(x5); // get back FPSR to check the IOC bit TBZ(x5, FPSR_IOC, 4+4); MOVw_REG(x1, x4); -- cgit 1.4.1