From 0c069aaba103391678dad04f528f93ee6a8984c5 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Thu, 6 Jan 2022 18:13:16 +0100 Subject: [DYNAREC] Oops, fixed 66 0F D1/D2 opcodes --- src/dynarec/dynarec_arm64_660f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/dynarec/dynarec_arm64_660f.c b/src/dynarec/dynarec_arm64_660f.c index 97d49ea5..b1640609 100755 --- a/src/dynarec/dynarec_arm64_660f.c +++ b/src/dynarec/dynarec_arm64_660f.c @@ -1527,7 +1527,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n GETGX(q0); GETEX(q1, 0); v0 = fpu_get_scratch(dyn); - VDUPQ_16(v0, q0, 0); + VDUPQ_16(v0, q1, 0); NEGQ_16(v0, v0); // neg, because SHR USHLQ_16(q0, q0, v0); // SHR x8 break; @@ -1537,7 +1537,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n GETGX(q0); GETEX(q1, 0); v0 = fpu_get_scratch(dyn); - VDUPQ_32(v0, q0, 0); + VDUPQ_32(v0, q1, 0); NEGQ_32(v0, v0); // neg, because SHR USHLQ_32(q0, q0, v0); // SHR x4 break; -- cgit 1.4.1