From 2604bb078cd6f554dcbe816b92dc344665f56afb Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Sun, 25 Jun 2023 15:12:42 +0200
Subject: [32BITS][ARM64_DYNAREC] Added (faked) 6D opcode

---
 src/dynarec/arm64/dynarec_arm64_00.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

(limited to 'src')

diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c
index 6eed0d31..2a5d4faf 100755
--- a/src/dynarec/arm64/dynarec_arm64_00.c
+++ b/src/dynarec/arm64/dynarec_arm64_00.c
@@ -750,6 +750,34 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             }
             break;
 
+        case 0x6D:
+            if(rex.is32bits) {
+                if(rep) {
+                    // Faking port read
+                    INST_NAME("REP INSD");
+                    CBZx_NEXT(xRCX);
+                    TBNZ_MARK2(xFlags, F_DF);
+                    MARK;   // Part with DF==0
+                    STRH_S9_postindex(xZR, xRDI, 4);
+                    SUBx_U12(xRCX, xRCX, 1);
+                    CBNZx_MARK(xRCX);
+                    B_NEXT_nocond;
+                    MARK2;  // Part with DF==1
+                    STRH_S9_postindex(xZR, xRDI, -4);
+                    SUBx_U12(xRCX, xRCX, 1);
+                    CBNZx_MARK2(xRCX);
+                    // done
+                } else {
+                    INST_NAME("INSD");
+                    GETDIR(x3, 4);
+                    STRH_U12(xZR, xRDI, 0);
+                    ADDx_REG(xRDI, xRDI, x3);
+                }
+            } else {
+                DEFAULT;
+            }
+            break;
+
         #define GO(GETFLAGS, NO, YES, F)                                \
             READFLAGS(F);                                               \
             i8 = F8S;                                                   \
-- 
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