From 2cd4d60325a194d6cd535bc5a9c873ab20c2ad51 Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Thu, 15 May 2025 20:30:18 +0800 Subject: [RV64_DYNAREC] Added F2 0F F0 LDDQU opcode for vector (#2639) --- src/dynarec/rv64/dynarec_rv64_f20f_vector.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src') diff --git a/src/dynarec/rv64/dynarec_rv64_f20f_vector.c b/src/dynarec/rv64/dynarec_rv64_f20f_vector.c index a75741b9..686ee717 100644 --- a/src/dynarec/rv64/dynarec_rv64_f20f_vector.c +++ b/src/dynarec/rv64/dynarec_rv64_f20f_vector.c @@ -573,6 +573,24 @@ uintptr_t dynarec64_F20F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i VMV_X_S(x4, d0); VMV_S_X(v0, x4); break; + case 0xF0: + INST_NAME("LDDQU Gx, Ex"); + nextop = F8; + GETG; + if (MODREG) { + SET_ELEMENT_WIDTH(x1, VECTOR_SEWANY, 1); + ed = (nextop & 7) + (rex.b << 3); + v1 = sse_get_reg_vector(dyn, ninst, x1, ed, 0, dyn->vector_eew); + v0 = sse_get_reg_empty_vector(dyn, ninst, x1, gd); + VMV_V_V(v0, v1); + } else { + SET_ELEMENT_WIDTH(x1, VECTOR_SEW8, 1); // unaligned! + SMREAD(); + v0 = sse_get_reg_empty_vector(dyn, ninst, x1, gd); + addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 0, 0); + VLE_V(v0, ed, dyn->vector_eew, VECTOR_UNMASKED, VECTOR_NFIELD1); + } + break; default: DEFAULT_VECTOR; } return addr; -- cgit 1.4.1