From 35f8500acdcb84568579db604f47d5cfdd532012 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Mon, 22 Mar 2021 17:54:43 +0100
Subject: [DYNAREC] Switched all other lock mecnism to LDAXR/STLXR

---
 src/dynarec/arm64_lock.S       | 24 ++++++++++++------------
 src/dynarec/dynarec_arm64_f0.c |  8 ++++----
 2 files changed, 16 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/dynarec/arm64_lock.S b/src/dynarec/arm64_lock.S
index 0eb4dff3..ed17ad54 100755
--- a/src/dynarec/arm64_lock.S
+++ b/src/dynarec/arm64_lock.S
@@ -19,55 +19,55 @@
 
 arm64_lock_read_b:
     // address is x0, return is x0
-    ldxrb   w0, [x0]
+    ldaxrb  w0, [x0]
     ret
 
 arm64_lock_write_b:
     // address is x0, value is x1, return is x0
     mov     x2, x0
-    stxrb   w0, w1, [x2]
+    stlxrb  w0, w1, [x2]
     ret
 
 arm64_lock_read_h:
     // address is x0, return is x0
-    ldxrh   w0, [x0]
+    ldaxrh  w0, [x0]
     ret
 
 arm64_lock_write_h:
     // address is x0, value is x1, return is x0
     mov     x2, x0
-    stxrh   w0, w1, [x2]
+    stlxrh  w0, w1, [x2]
     ret
 
 arm64_lock_read_d:
     // address is x0, return is x0
-    ldxr     w0, [x0]
+    ldaxr    w0, [x0]
     #ldx     w0,[x0]
     ret
 
 arm64_lock_write_d:
     // address is x0, value is w1, return is x0
     mov     x2, x0
-    stxr    w0, w1, [x2]
+    stlxr   w0, w1, [x2]
     #str     w1, [x2]
     mov     w0, 0
     ret
 
 arm64_lock_read_dd:
     // address is x0, return is x0
-    ldxr    x0, [x0]
+    ldaxr   x0, [x0]
     ret
 
 arm64_lock_write_dd:
     // address is x0, value is x1, return is x0
     mov     x2, x0
-    stxr    w0, x1, [x2]
+    stlxr   w0, x1, [x2]
     ret
 
 arm64_lock_xchg:
     // address is x0, value is x1, return old value in x0
-    ldxr    x2, [x0]
-    stxr    w3, x1, [x0]
+    ldaxr   x2, [x0]
+    stlxr   w3, x1, [x0]
     cmp     w3, #1
     beq     arm64_lock_xchg
     mov     x0, x2
@@ -75,11 +75,11 @@ arm64_lock_xchg:
 
 arm64_lock_storeifnull:
     // address is x0, value is x1, x1 store to x0 only if [x0] is 0. return new [x0] value (so x1 or old value)
-    ldxr    x2, [x0]
+    ldaxr   x2, [x0]
     cmp     x2, #0
     bne     arm64_lock_storeifnull_exit
     mov     x2, x1
-    stxr    w3, x2, [x0]
+    stlxr   w3, x2, [x0]
     cmp     w3, #1
     beq     arm64_lock_storeifnull
 arm64_lock_storeifnull_exit:
diff --git a/src/dynarec/dynarec_arm64_f0.c b/src/dynarec/dynarec_arm64_f0.c
index 8f24f917..39efcf2b 100644
--- a/src/dynarec/dynarec_arm64_f0.c
+++ b/src/dynarec/dynarec_arm64_f0.c
@@ -77,24 +77,24 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         B_MARK3(cNE);
                         // Aligned version
                         MARKLOCK;
-                        LDXRxw(x1, wback);
+                        LDAXRxw(x1, wback);
                         ed = x1;
                         CMPSxw_REG(xRAX, ed);
                         B_MARK(cNE);
                         // EAX == Ed
-                        STXRxw(x4, gd, wback);
+                        STLXRxw(x4, gd, wback);
                         CBNZx_MARKLOCK(x4);
                         // done
                         B_MARK_nocond;
                         // Unaligned version
                         MARK3;
                         LDRxw_U12(x1, wback, 0);
-                        LDXRB(x3, wback); // dummy read, to arm the write...
+                        LDAXRB(x3, wback); // dummy read, to arm the write...
                         ed = x1;
                         CMPSxw_REG(xRAX, ed);
                         B_MARK(cNE);
                         // EAX == Ed
-                        STXRB(x4, gd, wback);
+                        STLXRB(x4, gd, wback);
                         CBNZx_MARK3(x4);
                         STRxw_U12(gd, wback, 0);
                         B_MARK_nocond;
-- 
cgit 1.4.1