From 39568bff2fe3dc8d907d0738ccca4c14501cd808 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Mon, 20 Nov 2023 12:31:22 +0100 Subject: [ARM64_DYNAREC] Added D7 XLAT opcode --- src/dynarec/arm64/arm64_emitter.h | 1 + src/dynarec/arm64/dynarec_arm64_00.c | 10 ++++++++++ 2 files changed, 11 insertions(+) (limited to 'src') diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h index 79e24f02..23842f28 100644 --- a/src/dynarec/arm64/arm64_emitter.h +++ b/src/dynarec/arm64/arm64_emitter.h @@ -240,6 +240,7 @@ #define LDRxw_REG(Rt, Rn, Rm) EMIT(LDR_REG_gen(0b10+rex.w, Rm, 0b011, 0, Rn, Rt)) #define LDRz_REG(Rt, Rn, Rm) EMIT(LDR_REG_gen(rex.is32bits?0b10:0b11, Rm, 0b011, 0, Rn, Rt)) #define LDRB_REG(Rt, Rn, Rm) EMIT(LDR_REG_gen(0b00, Rm, 0b011, 0, Rn, Rt)) +#define LDRB_REG_UXTW(Rt, Rn, Rm) EMIT(LDR_REG_gen(0b00, Rm, 0b010, 0, Rn, Rt)) #define LDRH_REG(Rt, Rn, Rm) EMIT(LDR_REG_gen(0b01, Rm, 0b011, 0, Rn, Rt)) #define LDRS_U12_gen(size, op1, opc, imm12, Rn, Rt) ((size)<<30 | 0b111<<27 | (op1)<<24 | (opc)<<22 | (imm12)<<10 | (Rn)<<5 | (Rt)) diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c index 43d0cd52..622269b9 100644 --- a/src/dynarec/arm64/dynarec_arm64_00.c +++ b/src/dynarec/arm64/dynarec_arm64_00.c @@ -2547,6 +2547,16 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0xD7: + INST_NAME("XLAT"); + UXTBw(x1, xRAX); + if(rex.w || rex.is32bits) { + LDRB_REG(x1, xRBX, x1); + } else { + LDRB_REG_UXTW(x1, x1, xRBX); + } + BFIx(xRAX, x1, 0, 8); + break; case 0xD8: addr = dynarec64_D8(dyn, addr, ip, ninst, rex, rep, ok, need_epilog); break; -- cgit 1.4.1