From 3f641c2b67ae210caa6ebe7a6e4253038dada6a5 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Wed, 30 Mar 2022 12:17:52 +0200 Subject: Improved test17 ([DYNAREC] Added 66 0F 38 16 opcode, fixed 66 0F 38 24/34 opcodes) --- src/dynarec/arm64/dynarec_arm64_660f.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c index aa8a724a..c739ee15 100755 --- a/src/dynarec/arm64/dynarec_arm64_660f.c +++ b/src/dynarec/arm64/dynarec_arm64_660f.c @@ -385,7 +385,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n GETEX(q1, 0); GETGX_empty(q0); SXTL_16(q0, q1); // 16bits->32bits - SXTL_32(q0, q1); // 32bits->64bits + SXTL_32(q0, q0); // 32bits->64bits break; case 0x25: INST_NAME("PMOVSXDQ Gx, Ex"); // SSE4 opcode! @@ -432,7 +432,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n GETEX(q1, 0); GETGX_empty(q0); UXTL_16(q0, q1); // 16bits->32bits - UXTL_32(q0, q1); // 32bits->64bits + UXTL_32(q0, q0); // 32bits->64bits break; case 0x35: INST_NAME("PMOVZXDQ Gx, Ex"); // SSE4 opcode! @@ -451,7 +451,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n break; case 0x3D: - INST_NAME("PMINSD Gx, Ex"); // SSE4 opcode! + INST_NAME("PMAXSD Gx, Ex"); // SSE4 opcode! nextop = F8; GETEX(q1, 0); GETGX(q0); @@ -603,6 +603,19 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n } break; + case 0x16: + if(rex.w) {INST_NAME("PEXTRQ Ed, Gx, Ib");} else {INST_NAME("PEXTRD Ed, Gx, Ib");} + nextop = F8; + GETGX(q0); + GETED(1); + u8 = F8; + if(rex.w) { + VMOVQDto(ed, q0, (u8&1)); + } else { + VMOVSto(ed, q0, (u8&3)); + } + break; + case 0x22: INST_NAME("PINSRD Gx, ED, Ib"); nextop = F8; -- cgit 1.4.1