From 4aaa0b5d24fc3aad2032615ecf661cc0710b11bc Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Sat, 28 Dec 2024 12:10:13 +0100
Subject: [ARM64_DYNAREC] Fixed and improved flags for F3 0F B8 opcode

---
 src/dynarec/arm64/dynarec_arm64_f30f.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/dynarec/arm64/dynarec_arm64_f30f.c b/src/dynarec/arm64/dynarec_arm64_f30f.c
index e223f321..c13079f0 100644
--- a/src/dynarec/arm64/dynarec_arm64_f30f.c
+++ b/src/dynarec/arm64/dynarec_arm64_f30f.c
@@ -480,10 +480,18 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             UADDLV_8(v1, v1);
             VMOVQDto(gd, v1, 0);
             IFX(X_ALL) {
-                MOV32w(x1, (1<<F_OF) | (1<<F_SF) | (1<<F_ZF) | (1<<F_AF) | (1<<F_CF) | (1<<F_PF));
-                BICw(xFlags, xFlags, x1);
-                CBNZx(gd, 4+4);
-                BFIw(xFlags, xFlags, F_ZF, 1);
+                IFX(X_AF|X_PF|X_SF|X_OF|X_CF) {
+                    MOV32w(x1, (1<<F_OF) | (1<<F_SF) | (1<<F_ZF) | (1<<F_AF) | (1<<F_CF) | (1<<F_PF));
+                    BICw(xFlags, xFlags, x1);
+                }
+                IFX(X_ZF) {
+                    CMPSw_U12(gd, 0);
+                    IFNATIVE(NF_EQ) {}
+                    else {
+                        CSETw(x1, cEQ);
+                        BFIw(xFlags, x1, F_ZF, 1);
+                    }                    
+                }
             }
             break;
 
-- 
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