From 4f04deadfe75c5cbf4e135200a5f27764ec0b0e5 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Tue, 15 Apr 2025 14:12:29 +0200 Subject: [ARM64_DYNAREC] Added 67 0F 29 opcode --- src/dynarec/arm64/dynarec_arm64_67.c | 16 ++++++++++++++++ src/dynarec/arm64/dynarec_arm64_67_32.c | 25 +++++++++++++++++++++++++ 2 files changed, 41 insertions(+) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_67.c b/src/dynarec/arm64/dynarec_arm64_67.c index 3d9a7b35..d70da391 100644 --- a/src/dynarec/arm64/dynarec_arm64_67.c +++ b/src/dynarec/arm64/dynarec_arm64_67.c @@ -197,6 +197,22 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0x29: + INST_NAME("MOVAPS Ex,Gx"); + nextop = F8; + GETG; + v0 = sse_get_reg(dyn, ninst, x1, gd, 0); + if(MODREG) { + ed = (nextop&7)+(rex.b<<3); + v1 = sse_get_reg_empty(dyn, ninst, x1, ed); + VMOVQ(v1, v0); + } else { + addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0); + VST128(v0, ed, fixedaddress); + SMWRITE2(); + } + break; + case 0x2E: // no special check... case 0x2F: diff --git a/src/dynarec/arm64/dynarec_arm64_67_32.c b/src/dynarec/arm64/dynarec_arm64_67_32.c index c927efbd..477b41be 100644 --- a/src/dynarec/arm64/dynarec_arm64_67_32.c +++ b/src/dynarec/arm64/dynarec_arm64_67_32.c @@ -59,6 +59,31 @@ uintptr_t dynarec64_67_32(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int switch(opcode) { + case 0x0F: + opcode=F8; + switch(opcode) { + + case 0x29: + INST_NAME("MOVAPS Ex,Gx"); + nextop = F8; + GETG; + v0 = sse_get_reg(dyn, ninst, x1, gd, 0); + if(MODREG) { + ed = (nextop&7)+(rex.b<<3); + v1 = sse_get_reg_empty(dyn, ninst, x1, ed); + VMOVQ(v1, v0); + } else { + addr = geted16(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, 0); + VST128(v0, ed, fixedaddress); + SMWRITE2(); + } + break; + + default: + DEFAULT; + } + break; + case 64: addr = dynarec64_6764_32(dyn, addr, ip, ninst, rex, rep, _FS, ok, need_epilog); break; -- cgit 1.4.1