From 50cf9c0e67936c1b5051ecab777cf8a5be1481a3 Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Tue, 12 Sep 2023 22:08:12 +0800 Subject: [CI] Test RISCV with bit-manipulation extensions on (#972) * [CI] Test RISCV with bit-manipulation extensions on xthead extensions require qemu 8.1.0, therefore not available in CI * fix ADDSL --- src/dynarec/rv64/rv64_emitter.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/dynarec/rv64/rv64_emitter.h b/src/dynarec/rv64/rv64_emitter.h index 23f4f73d..4eebb353 100644 --- a/src/dynarec/rv64/rv64_emitter.h +++ b/src/dynarec/rv64/rv64_emitter.h @@ -311,7 +311,7 @@ f28–31 ft8–11 FP temporaries Caller #define ADDIz(rd, rs1, imm12) EMIT(I_type((imm12)&0b111111111111, rs1, 0b000, rd, rex.is32bits?0b0011011:0b0010011)) // rd = rs1 + (rs2 << imm2) -#define ADDSL(rd, rs1, rs2, imm2, scratch) if (!imm2) { \ +#define ADDSL(rd, rs1, rs2, imm2, scratch) if (!(imm2)) { \ ADD(rd, rs1, rs2); \ } else if (rv64_zba) { \ SHxADD(rd, rs2, imm2, rs1); \ -- cgit 1.4.1