From 64fdf541561d9c8858e2498ef18587c00964ee17 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Sat, 2 Mar 2024 16:36:54 +0100
Subject: [ARM64_DYNAREC] Fixed flags for 69 opcode, and small optim for 0F AF
 opcode

---
 src/dynarec/arm64/dynarec_arm64_00.c | 55 +++++++++++++++---------------------
 src/dynarec/arm64/dynarec_arm64_0f.c | 18 ++++++++----
 2 files changed, 36 insertions(+), 37 deletions(-)

(limited to 'src')

diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c
index 86d1b83d..527c21ba 100644
--- a/src/dynarec/arm64/dynarec_arm64_00.c
+++ b/src/dynarec/arm64/dynarec_arm64_00.c
@@ -836,29 +836,24 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     IFX(X_PEND) {
                         UFLAG_OP1(x3);
                         UFLAG_RES(gd);
-                        UFLAG_DF(x3, d_imul64);
+                        UFLAG_DF(x1, d_imul64);
                     } else {
-                        SET_DFNONE(x3);
+                        SET_DFNONE(x1);
                     }
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
                     }
                     IFX(X_CF | X_OF) {
-                        MOV64x(x1, 0xffffffffffffffffLL);
-                        CBZx_MARK3(x3);
-                        CMPSx_REG(x3, x1);
-                        B_MARK2(cNE);
-                        MARK3;
-                        EORx_REG(x1, x1, x3); //bit 63 should be 0 after the xor
-                        TBNZ_MARK2(x1, 63);
-                        BFCw(xFlags, F_CF, 1);
-                        BFCw(xFlags, F_OF, 1);
-                        B_NEXT_nocond;
-                        MARK2;
-                        MOV32w(x1, 1);
-                        BFIw(xFlags, x1, F_CF, 1);
-                        BFIw(xFlags, x1, F_OF, 1);
+                        ASRx(x4, gd, 63);
+                        CMPSx_REG(x3, x4);
+                        CSETw(x1, cNE);
+                        IFX(X_CF) {
+                            BFIw(xFlags, x1, F_CF, 1);
+                        }
+                        IFX(X_OF) {
+                            BFIw(xFlags, x1, F_OF, 1);
+                        }
                     }
                 } else {
                     MULxw(gd, ed, x4);
@@ -872,29 +867,25 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     MOVw_REG(gd, gd);
                     IFX(X_PEND) {
                         UFLAG_OP1(x3);
-                        UFLAG_DF(x3, d_imul32);
+                        UFLAG_DF(x1, d_imul32);
                     } else {
-                        SET_DFNONE(x3);
+                        SET_DFNONE(x1);
                     }
                     IFX(X_ZF | X_PF | X_AF | X_SF) {
                         MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
                         BICw(xFlags, xFlags, x1);
                     }
                     IFX(X_CF | X_OF) {
-                        MOV32w(x1, 0xffffffff);
-                        CBZw_MARK3(x3);
-                        CMPSw_REG(x3, x1);
-                        B_MARK2(cNE);
-                        MARK3;
-                        EORw_REG(x1, x1, x3); //bit 63 should be 0 after the xor
-                        TBNZ_MARK2(x1, 31);
-                        BFCw(xFlags, F_CF, 1);
-                        BFCw(xFlags, F_OF, 1);
-                        B_NEXT_nocond;
-                        MARK2;
-                        MOV32w(x1, 1);
-                        BFIw(xFlags, x1, F_CF, 1);
-                        BFIw(xFlags, x1, F_OF, 1);
+                        ASRw(x3, x3, 31);
+                        ASRw(x4, gd, 31);
+                        CMPSw_REG(x3, x4);
+                        CSETw(x3, cNE);
+                        IFX(X_CF) {
+                            BFIw(xFlags, x1, F_CF, 1);
+                        }
+                        IFX(X_OF) {
+                            BFIw(xFlags, x1, F_OF, 1);
+                        }
                     }
                 } else {
                     MULxw(gd, ed, x4);
diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c
index 2b7892e5..0d857fba 100644
--- a/src/dynarec/arm64/dynarec_arm64_0f.c
+++ b/src/dynarec/arm64/dynarec_arm64_0f.c
@@ -1833,8 +1833,12 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         ASRx(x4, gd, 63);
                         CMPSx_REG(x3, x4);
                         CSETw(x3, cNE);
-                        BFIw(xFlags, x3, F_CF, 1);
-                        BFIw(xFlags, x3, F_OF, 1);
+                        IFX(X_CF) {
+                            BFIw(xFlags, x3, F_CF, 1);
+                        }
+                        IFX(X_OF) {
+                            BFIw(xFlags, x3, F_OF, 1);
+                        }
                     }
                 } else {
                     MULxw(gd, gd, ed);
@@ -1852,12 +1856,16 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         SET_DFNONE(x4);
                     }
                     IFX(X_CF|X_OF) {
-                        ASRx(x3, gd, 31);
+                        ASRx(x3, gd, 63);
                         ASRw(x4, gd, 31);
                         CMPSw_REG(x3, x4);
                         CSETw(x3, cNE);
-                        BFIw(xFlags, x3, F_CF, 1);
-                        BFIw(xFlags, x3, F_OF, 1);
+                        IFX(X_CF) {
+                            BFIw(xFlags, x3, F_CF, 1);
+                        }
+                        IFX(X_OF) {
+                            BFIw(xFlags, x3, F_OF, 1);
+                        }
                     }
                     if(box64_dynarec_test) {
                         // to avoid noise during test
-- 
cgit 1.4.1