From 735d9c107d5054019ef89367256a6df1a01edda7 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Mon, 22 Mar 2021 16:14:59 +0100
Subject: [DYNAREC] Added F2 0F 5A opcode

---
 src/dynarec/arm64_emitter.h      | 4 ++++
 src/dynarec/arm64_printer.c      | 9 +++++++++
 src/dynarec/dynarec_arm64_f20f.c | 9 +++++++++
 3 files changed, 22 insertions(+)

(limited to 'src')

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index 7313854a..4d39a2d3 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -843,6 +843,10 @@
 #define VFCVTZUQS(Vd, Vn)           EMIT(FCVT2_vector(1, 1, 1, 0, 1, Vn, Vd))
 #define VFCVTZUQD(Vd, Vn)           EMIT(FCVT2_vector(1, 1, 1, 1, 1, Vn, Vd))
 
+#define FCVT_precision(type, opc, Rn, Rd)   (0b11110<<24 | (type)<<22 | 1<<21 | 0b0001<<17 | (opc)<<15 | 0b10000<<10 | (Rn)<<5 | (Rd))
+#define FCVT_D_S(Dd, Sn)            EMIT(FCVT_precision(0b00, 0b01, Sn, Dd))
+#define FCVT_S_D(Sd, Dn)            EMIT(FCVT_precision(0b01, 0b00, Dn, Sd))
+
 #define SCVTF_scalar(sf, type, rmode, opcode, Rn, Rd)   ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (rmode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
 #define SCVTSw(Sd, Wn)              EMIT(SCVTF_scalar(0, 0b00, 0b00, 0b010, Wn, Sd))
 #define SCVTDw(Dd, Wn)              EMIT(SCVTF_scalar(0, 0b00, 0b01, 0b010, Wn, Dd))
diff --git a/src/dynarec/arm64_printer.c b/src/dynarec/arm64_printer.c
index e217726e..4a4e8247 100755
--- a/src/dynarec/arm64_printer.c
+++ b/src/dynarec/arm64_printer.c
@@ -945,6 +945,15 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         return buff;
     }
 
+    if(isMask(opcode, "0001111000100010110000nnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "FCVT D%d, S%d", Rd, Rn);
+        return buff;
+    }
+    if(isMask(opcode, "0001111001100010010000nnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "FCVT S%d, D%d", Rd, Rn);
+        return buff;
+    }
+
     // FMOV
     if(isMask(opcode, "00011110pp100000010000nnnnnddddd", &a)) {
         int type = a.p;
diff --git a/src/dynarec/dynarec_arm64_f20f.c b/src/dynarec/dynarec_arm64_f20f.c
index 906f8bc8..82388dd4 100755
--- a/src/dynarec/dynarec_arm64_f20f.c
+++ b/src/dynarec/dynarec_arm64_f20f.c
@@ -127,6 +127,15 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             FMULD(d1, v0, d0);
             VMOVeD(v0, 0, d1, 0);
             break;
+        case 0x5A:
+            INST_NAME("CVTSD2SS Gx, Ex");
+            nextop = F8;
+            GETGX(v0);
+            GETEX(d0, 0);
+            d1 = fpu_get_scratch(dyn);
+            FCVT_D_S(d1, d0);
+            VMOVeS(v0, 0, d1, 0);
+            break;
 
         case 0x5C:
             INST_NAME("SUBSD Gx, Ex");
-- 
cgit 1.4.1