From 78b9b0cec8ad87e4ac982465a9270e570d146e4f Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Mon, 12 Jul 2021 10:35:04 -0500 Subject: [DYNAREC] Fixed shrd/shld emiter when both regs are the same (for #33) --- src/dynarec/dynarec_arm64_emit_shift.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/dynarec/dynarec_arm64_emit_shift.c b/src/dynarec/dynarec_arm64_emit_shift.c index 0380650d..e8f3d376 100755 --- a/src/dynarec/dynarec_arm64_emit_shift.c +++ b/src/dynarec/dynarec_arm64_emit_shift.c @@ -368,8 +368,8 @@ void emit_shrd32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int3 } BFIw(xFlags, s3, 0, 1); } - LSRxw(s1, s1, c); - ORRxw_REG_LSL(s1, s1, s2, (rex.w?64:32)-c); + LSRxw(s3, s1, c); + ORRxw_REG_LSL(s1, s3, s2, (rex.w?64:32)-c); IFX(X_PEND) { STRxw_U12(s1, xEmu, offsetof(x64emu_t, res)); } @@ -419,8 +419,8 @@ void emit_shld32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int3 LSRxw(s3, s1, (rex.w?64:32)-c); BFIxw(xFlags, s3, F_CF, 1); } - LSLxw(s1, s1, c); - ORRxw_REG_LSR(s1, s1, s2, (rex.w?64:32)-c); + LSLxw(s3, s1, c); + ORRxw_REG_LSR(s1, s3, s2, (rex.w?64:32)-c); IFX(X_PEND) { STRxw_U12(s1, xEmu, offsetof(x64emu_t, res)); -- cgit 1.4.1