From 83104b32b8380f9a6dcfe736a123c488cb06528c Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Mon, 22 Mar 2021 13:55:00 +0100 Subject: [DYNAREC] Added 98/99 opcodes --- src/dynarec/arm64_emitter.h | 4 ++++ src/dynarec/dynarec_arm64_00.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) (limited to 'src') diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h index c94fe57f..7f78659b 100755 --- a/src/dynarec/arm64_emitter.h +++ b/src/dynarec/arm64_emitter.h @@ -467,10 +467,14 @@ #define SXTBw(Rd, Rn) SBFMw(Rd, Rn, 0, 7) #define SXTHx(Rd, Rn) SBFMx(Rd, Rn, 0, 15) #define SXTHw(Rd, Rn) SBFMw(Rd, Rn, 0, 15) +#define SXTHxw(Rd, Rn) SBFMxw(Rd, Rn, 0, 15) #define SXTWx(Rd, Rn) SBFMx(Rd, Rn, 0, 31) #define ASRx(Rd, Rn, shift) SBFMx(Rd, Rn, shift, 63) #define ASRw(Rd, Rn, shift) SBFMw(Rd, Rn, shift, 31) #define ASRxw(Rd, Rn, shift) SBFMxw(Rd, Rn, shift, rex.w?63:31) +#define SBFIZx(Rd, Rn, lsb, width) SFBFMx(Rd, Rn, ((-(lsb))%64), (width)-1) +#define SBFIZw(Rd, Rn, lsb, width) SFBFMw(Rd, Rn, ((-(lsb))%32), (width)-1) +#define SBFIZxw(Rd, Rn, lsb, width) SFBFMxw(Rd, Rn, ((-(lsb))%(rex.w?64:32)), (width)-1) // EXTR #define EXTR_gen(sf, N, Rm, imms, Rn, Rd) ((sf)<<31 | 0b00<<29 | 0b100111<<23 | (N)<<22 | (Rm)<<16 | (imms)<<10 | (Rn)<<5 | (Rd)) diff --git a/src/dynarec/dynarec_arm64_00.c b/src/dynarec/dynarec_arm64_00.c index c388e4f3..2fb108b2 100755 --- a/src/dynarec/dynarec_arm64_00.c +++ b/src/dynarec/dynarec_arm64_00.c @@ -939,6 +939,19 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin INST_NAME("NOP"); break; + case 0x98: + INST_NAME("CWDE"); + if(rex.w) { + SXTWx(xRAX, xRAX); + } else { + SXTHw(xRAX, xRAX); + } + break; + case 0x99: + INST_NAME("CDQ"); + SBFXxw(xRDX, xRAX, rex.w?63:31, 1); + break; + case 0x9B: INST_NAME("FWAIT"); break; -- cgit 1.4.1