From 8ef63665f48b8323f08c5e23cedd5df3b387348b Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Fri, 5 Mar 2021 12:09:26 +0100
Subject: Added REX 0F 80..8F Jcc opcodes

---
 src/emu/x64run0f.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src')

diff --git a/src/emu/x64run0f.c b/src/emu/x64run0f.c
index 31b22eec..cdaf3e4a 100644
--- a/src/emu/x64run0f.c
+++ b/src/emu/x64run0f.c
@@ -31,6 +31,7 @@ int Run0F(x64emu_t *emu, rex_t rex)
 {
     uint8_t opcode;
     uint8_t nextop;
+    int32_t tmp32s;
     reg64_t *oped, *opgd;
 
     opcode = F8;
@@ -55,6 +56,11 @@ int Run0F(x64emu_t *emu, rex_t rex)
             , if(rex.w) {GD->q[0] = ED->q[0]; } else {GD->dword[0] = ED->dword[0];}
         )                               /* 0x40 -> 0x4F CMOVxx Gd,Ed */ // conditional move, no sign
         
+        GOCOND(0x80
+            , tmp32s = F32S; CHECK_FLAGS(emu);
+            , R_RIP += tmp32s;
+        )                               /* 0x80 -> 0x8F Jxx */
+
         case 0xAF:                      /* IMUL Gd,Ed */
             nextop = F8;
             GETED;
-- 
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