From 8f3018e10ce4e77053c839758f8e2bc42b6bfb11 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Tue, 15 Apr 2025 14:15:03 +0200 Subject: [ARM64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and cosim scenario --- src/dynarec/arm64/dynarec_arm64_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_helper.c b/src/dynarec/arm64/dynarec_arm64_helper.c index fb52d141..e8aa70c2 100644 --- a/src/dynarec/arm64/dynarec_arm64_helper.c +++ b/src/dynarec/arm64/dynarec_arm64_helper.c @@ -1307,7 +1307,7 @@ static void x87_reflectcache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int if(dyn->n.x87cache[i]!=-1) { ADDw_U12(s3, s2, dyn->n.x87cache[i]); ANDw_mask(s3, s3, 0, 2); // mask=7 // (emu->top + i)&7 - if(neoncache_get_st_f(dyn, ninst, dyn->n.x87cache[i])>=0) { + if(neoncache_get_current_st_f(dyn, dyn->n.x87cache[i])>=0) { int scratch = fpu_get_scratch(dyn, ninst); FCVT_D_S(scratch, dyn->n.x87reg[i]); VSTR64_REG_LSL3(scratch, s1, s3); -- cgit 1.4.1