From 8f719b7fede4d50050ee2633f94efda80fc830f0 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sun, 25 Jun 2023 18:17:09 +0200 Subject: [ARM64_DYNAREC] Added (F2/F3) 66 A7 opcode --- src/dynarec/arm64/dynarec_arm64_66.c | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_66.c b/src/dynarec/arm64/dynarec_arm64_66.c index e72d58d4..7a9a27cb 100755 --- a/src/dynarec/arm64/dynarec_arm64_66.c +++ b/src/dynarec/arm64/dynarec_arm64_66.c @@ -601,6 +601,46 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0xA7: + switch(rep) { + case 1: + case 2: + if(rep==1) {INST_NAME("REPNZ CMPSW");} else {INST_NAME("REPZ CMPSW");} + MAYSETFLAGS(); + SETFLAGS(X_ALL, SF_SET_PENDING); + CBZx_NEXT(xRCX); + TBNZ_MARK2(xFlags, F_DF); + MARK; // Part with DF==0 + LDRH_S9_postindex(x1, xRSI, 2); + LDRH_S9_postindex(x2, xRDI, 2); + SUBx_U12(xRCX, xRCX, 1); + CMPSw_REG(x1, x2); + B_MARK3((rep==1)?cEQ:cNE); + CBNZx_MARK(xRCX); + B_MARK3_nocond; + MARK2; // Part with DF==1 + LDRH_S9_postindex(x1, xRSI, -2); + LDRH_S9_postindex(x2, xRDI, -2); + SUBx_U12(xRCX, xRCX, 1); + CMPSw_REG(x1, x2); + B_MARK3((rep==1)?cEQ:cNE); + CBNZx_MARK2(xRCX); + MARK3; // end + emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5); + break; + default: + INST_NAME("CMPSW"); + SETFLAGS(X_ALL, SF_SET_PENDING); + GETDIR(x3, 2); + LDRH_U12(x1, xRSI, 0); + LDRH_U12(x2, xRDI, 0); + ADDx_REG(xRSI, xRSI, x3); + ADDx_REG(xRDI, xRDI, x3); + emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5); + break; + } + break; + case 0xA9: INST_NAME("TEST AX,Iw"); SETFLAGS(X_ALL, SF_SET_PENDING); -- cgit 1.4.1