From 9bc9c10fb3e98406d754da482a0901472671f859 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Fri, 9 Aug 2024 14:30:21 +0200 Subject: [ARM64_DYNAREC] Added AVX.66.0F38 9A opcode --- src/dynarec/arm64/dynarec_arm64_avx_66_0f38.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_avx_66_0f38.c b/src/dynarec/arm64/dynarec_arm64_avx_66_0f38.c index 7e41bec5..e8af6c6e 100644 --- a/src/dynarec/arm64/dynarec_arm64_avx_66_0f38.c +++ b/src/dynarec/arm64/dynarec_arm64_avx_66_0f38.c @@ -1208,7 +1208,18 @@ uintptr_t dynarec64_AVX_66_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip } YMM0(gd); break; - + case 0x9A: + INST_NAME("VFNMSUB132PS/D Gx, Vx, Ex"); + nextop = F8; + q0 = fpu_get_scratch(dyn, ninst); + for(int l=0; l<1+vex.l; ++l) { + if(!l) { GETGX_VXEX(v0, v2, v1, 0); } else { GETGY_VYEY(v0, v2, v1); } + if(rex.w) VFNEGQD(q0, v2); else VFNEGQS(q0, v2); + if(rex.w) VFMLAQD(q0, v0, v1); else VFMLAQS(q0, v0, v1); + VMOVQ(v0, q0); + } + if(!vex.l) YMM0(gd); + break; case 0x9B: INST_NAME("VFMSUB132SS/D Gx, Vx, Ex"); nextop = F8; @@ -1233,7 +1244,7 @@ uintptr_t dynarec64_AVX_66_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip if(!l && v0!=v2) q0 = fpu_get_scratch(dyn, ninst); if(v0!=v2) VMOVQ(q0, v2); else q0 = v2; if(rex.w) VFMLSQD(q0, v0, v1); else VFMLSQS(q0, v0, v1); - VMOVQ(v0, q0); + if(q0!=v0) VMOVQ(v0, q0); } if(!vex.l) YMM0(gd); break; -- cgit 1.4.1