From 9f0f1efafec5c310007997a345b8045ce218925f Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Wed, 31 Mar 2021 21:22:42 +0200
Subject: [DYNAREC] Added 0F E5 opcode

---
 src/dynarec/dynarec_arm64_0f.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src')

diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c
index da884b1a..7164b168 100755
--- a/src/dynarec/dynarec_arm64_0f.c
+++ b/src/dynarec/dynarec_arm64_0f.c
@@ -1230,6 +1230,16 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             VMUL_16(q0, q0, q1);
             break;
 
+        case 0xE5:
+            INST_NAME("PMULHW Gm,Em");
+            nextop = F8;
+            GETGM(v0);
+            GETEM(v1, 0);
+            q0 = fpu_get_scratch(dyn);
+            VSMULL_16(q0, v0, v1);
+            SQSHRN_16(v0, q0, 16);
+            break;
+
         case 0xEB:
             INST_NAME("POR Gm, Em");
             nextop = F8;
-- 
cgit 1.4.1